Alternatives and similar repositories for swerv_eh1:

Users that are interested in swerv_eh1 are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆869Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,049Updated 2 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆649Updated 5 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆697Updated last month
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆871Updated 4 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆529Updated 3 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,514Updated 3 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 3 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆597Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,097Updated 2 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆908Updated 5 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆997Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆606Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆523Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 8 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆712Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆419Updated last month
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆490Updated 5 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,256Updated 2 weeks ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆682Updated last month
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆322Updated 3 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆571Updated 8 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆568Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆480Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆544Updated last week
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆484Updated 2 months ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆947Updated last year