A directory of Western Digital’s RISC-V SweRV Cores
☆882Mar 26, 2020Updated 6 years ago
Alternatives and similar repositories for swerv_eh1
Users that are interested in swerv_eh1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆205Dec 3, 2020Updated 5 years ago
- VeeR EH1 core☆962Jul 16, 2026Updated last month
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,073Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆997Nov 15, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,277May 29, 2026Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,351Jul 31, 2026Updated 3 weeks ago
- The root repo for lowRISC project and FPGA demos.☆601Aug 3, 2023Updated 3 years ago
- Rocket Chip Generator☆3,850Jun 2, 2026Updated 2 months ago
- An open standard Cache Coherent Fabric Interface repository☆66Dec 6, 2019Updated 6 years ago
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,599May 12, 2026Updated 3 months ago
- VeeR EL2 Core☆344Updated this week
- RISC-V CPU Core☆444Jun 24, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Random instruction generator for RISC-V processor verification☆1,347Apr 3, 2026Updated 4 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,233Feb 11, 2026Updated 6 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,224Aug 11, 2026Updated last week
- Source files for SiFive's Freedom platforms☆1,146Jul 17, 2026Updated last month
- An open-source microcontroller system based on RISC-V☆1,060Feb 6, 2024Updated 2 years ago
- VeeR EH2 core☆276Jul 20, 2026Updated last month
- RTL, Cmodel, and testbench for NVDLA☆2,141Mar 2, 2022Updated 4 years ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,023Updated this week
- GPGPU microprocessor architecture☆2,217Nov 8, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 5 years ago
- A small, light weight, RISC CPU soft core☆1,575Updated this week
- SERV - The SErial RISC-V CPU☆1,869Jul 10, 2026Updated last month
- The OpenPiton Platform☆810Feb 25, 2026Updated 5 months ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,195Updated this week
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆382Oct 19, 2023Updated 2 years ago
- A Linux-capable RISC-V multicore for and by the world☆827Jul 13, 2026Updated last month
- mor1kx - an OpenRISC 1000 processor IP core☆586Jun 6, 2026Updated 2 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,452Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FuseSoC-based SoC for VeeR EH1 and EL2☆342Dec 11, 2024Updated last year
- Open Processor Architecture☆26Apr 7, 2016Updated 10 years ago
- An open source GPU based off of the AMD Southern Islands ISA.☆1,404Aug 18, 2025Updated last year
- Yosys Open SYnthesis Suite☆4,702Updated this week
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 3 years ago
- RISC-V Cores, SoC platforms and SoCs☆927Mar 26, 2021Updated 5 years ago
- educational microarchitectures for risc-v isa☆754Sep 1, 2025Updated 11 months ago