SpinalHDL / VexRiscvLinks
A FPGA friendly 32 bit RISC-V CPU implementation
☆2,842Updated last month
Alternatives and similar repositories for VexRiscv
Users that are interested in VexRiscv are comparing it to the libraries listed below
Sorting:
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,618Updated last year
- SERV - The SErial RISC-V CPU☆1,627Updated 2 months ago
- A small, light weight, RISC CPU soft core☆1,444Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,386Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,579Updated this week
- Scala based HDL☆1,840Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,605Updated last week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,828Updated last week
- 32-bit Superscalar RISC-V CPU☆1,080Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,954Updated 3 months ago
- Verilog library for ASIC and FPGA designers☆1,327Updated last year
- RISC-V CPU Core (RV32IM)☆1,516Updated 3 years ago
- Build your hardware, easily!☆3,452Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,105Updated 2 months ago
- Rocket Chip Generator☆3,514Updated 2 months ago
- VeeR EH1 core☆889Updated 2 years ago
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,930Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,322Updated last month
- cocotb: Python-based chip (RTL) verification☆2,056Updated this week
- nextpnr portable FPGA place and route tool☆1,491Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,095Updated 5 months ago
- Random instruction generator for RISC-V processor verification☆1,152Updated 2 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,132Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- Linux on LiteX-VexRiscv☆655Updated last month
- Verilator open-source SystemVerilog simulator and lint system☆3,030Updated this week
- OpenXuantie - OpenC910 Core☆1,299Updated last year
- An open-source microcontroller system based on RISC-V☆970Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆925Updated 9 months ago