Alternatives and similar repositories for VexRiscv

Users that are interested in VexRiscv are comparing it to the libraries listed below

• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,667Updated last year
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,403Updated 2 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,641Updated 3 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,459Updated last month
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,848Updated last week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,611Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,848Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,628Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,094Updated 3 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,969Updated 4 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,537Updated 3 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,338Updated last year
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,489Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,062Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,966Updated this week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,549Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,117Updated 3 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,075Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,341Updated last week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆894Updated 4 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆655Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,166Updated 3 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,515Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated 2 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,016Updated this week
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,598Updated last month
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆974Updated last year
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,157Updated this week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆992Updated last month