syntacore / scr1Links
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
☆933Updated 10 months ago
Alternatives and similar repositories for scr1
Users that are interested in scr1 are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,117Updated 3 months ago
- VeeR EH1 core☆894Updated 2 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated 2 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,091Updated 3 years ago
- Common SystemVerilog components☆654Updated last week
- Random instruction generator for RISC-V processor verification☆1,166Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,369Updated last week
- SystemVerilog to Verilog conversion☆665Updated 2 months ago
- RISC-V Cores, SoC platforms and SoCs☆894Updated 4 years ago
- Bus bridges and other odds and ends☆587Updated 5 months ago
- Various HDL (Verilog) IP Cores☆832Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆592Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆734Updated 3 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆510Updated 9 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆605Updated last week
- RISC-V CPU Core☆375Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆440Updated 4 months ago
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- The OpenPiton Platform☆730Updated this week
- RISC-V Formal Verification Framework☆609Updated 3 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆553Updated 3 weeks ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆593Updated 7 years ago
- OpenXuantie - OpenC910 Core☆1,314Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆527Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,459Updated last month
- Verilog UART☆505Updated 6 months ago
- ☆589Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆830Updated 6 months ago
- synthesiseable ieee 754 floating point library in verilog☆671Updated 2 years ago