Alternatives and similar repositories for riscv-dv:

Users that are interested in riscv-dv are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,023Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,491Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆860Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆961Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,233Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆597Updated 2 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆707Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆587Updated 2 weeks ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆863Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆902Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆667Updated 2 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆546Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆563Updated 7 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,017Updated 6 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆813Updated this week
• riscv-software-src / riscv-tests
  ☆950Updated 2 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,780Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆672Updated last week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆714Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆460Updated last month
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,394Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆559Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆405Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆481Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆478Updated 3 weeks ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,840Updated last week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆409Updated this week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆738Updated 6 months ago