Alternatives and similar repositories for riscv-formal

Users that are interested in riscv-formal are comparing it to the libraries listed below

• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆720Updated last month
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆556Updated 2 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,133Updated 5 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆902Updated 2 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 3 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆742Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆734Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆389Updated 4 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,180Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 5 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆598Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆613Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆666Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆298Updated 2 years ago
• riscv-non-isa / riscv-arch-test
  ☆599Updated this week
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆600Updated 2 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆603Updated 2 weeks ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆872Updated 5 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆938Updated 11 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆363Updated 8 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆328Updated 10 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆534Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆302Updated 3 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆350Updated last month