YosysHQ / picorv32Links
PicoRV32 - A Size-Optimized RISC-V CPU
☆3,703Updated last year
Alternatives and similar repositories for picorv32
Users that are interested in picorv32 are comparing it to the libraries listed below
Sorting:
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,886Updated 3 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,416Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,655Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,635Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,628Updated last week
- A small, light weight, RISC CPU soft core☆1,466Updated last month
- Scala based HDL☆1,853Updated this week
- RISC-V CPU Core (RV32IM)☆1,547Updated 4 years ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,866Updated last week
- Rocket Chip Generator☆3,566Updated last month
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- nextpnr portable FPGA place and route tool☆1,528Updated this week
- Random instruction generator for RISC-V processor verification☆1,175Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,344Updated 3 weeks ago
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,102Updated 4 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,979Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,123Updated 4 months ago
- The Ultra-Low Power RISC-V Core☆1,617Updated 2 months ago
- cocotb: Python-based chip (RTL) verification☆2,102Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,180Updated this week
- Yosys Open SYnthesis Suite☆4,053Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,986Updated this week
- Build your hardware, easily!☆3,533Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,092Updated this week
- VeeR EH1 core☆898Updated 2 years ago
- ☆1,064Updated 3 months ago
- An open-source microcontroller system based on RISC-V☆976Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆935Updated 10 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆994Updated last month