The root repo for lowRISC project and FPGA demos.
☆600Aug 3, 2023Updated 2 years ago
Alternatives and similar repositories for lowrisc-chip
Users that are interested in lowrisc-chip are comparing it to the libraries listed below
Sorting:
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Oct 2, 2019Updated 6 years ago
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- An open-source microcontroller system based on RISC-V☆1,012Feb 6, 2024Updated 2 years ago
- FPGA demo for Digilent NEXYS 4 board☆22Oct 2, 2019Updated 6 years ago
- RISC-V CPU Core☆417Jun 24, 2025Updated 8 months ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,845Mar 10, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆966Nov 15, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,105Mar 11, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,063Feb 11, 2026Updated last month
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 5 years ago
- RISC-V Formal Verification Framework☆625Apr 6, 2022Updated 3 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Chisel: A Modern Hardware Design Language☆4,611Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆684Jul 16, 2025Updated 8 months ago
- Support for Rocket Chip on Zynq FPGAs☆417Jan 29, 2019Updated 7 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,797Feb 17, 2026Updated last month
- mor1kx - an OpenRISC 1000 processor IP core☆578Aug 21, 2025Updated 7 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,182Dec 22, 2022Updated 3 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- ☆110Oct 19, 2018Updated 7 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,001Mar 9, 2026Updated last week
- ☆246Nov 30, 2016Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- VeeR EH1 core☆930May 29, 2023Updated 2 years ago
- chisel tutorial exercises and answers☆748Jan 6, 2022Updated 4 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆417Feb 20, 2026Updated last month
- Documentation for the BOOM processor☆47Mar 8, 2017Updated 9 years ago
- GPGPU microprocessor architecture☆2,180Nov 8, 2024Updated last year
- RTL, Cmodel, and testbench for NVDLA☆2,031Mar 2, 2022Updated 4 years ago
- RISC-V Linux Port☆607Apr 12, 2019Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,397May 8, 2024Updated last year
- ☆33Oct 4, 2017Updated 8 years ago
- OpenTitan: Open source silicon root of trust☆3,238Updated this week