The root repo for lowRISC project and FPGA demos.
☆601Aug 3, 2023Updated 2 years ago
Alternatives and similar repositories for lowrisc-chip
Users that are interested in lowrisc-chip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆55Oct 2, 2019Updated 6 years ago
- Rocket Chip Generator☆3,750Apr 21, 2026Updated last week
- An open-source microcontroller system based on RISC-V☆1,029Feb 6, 2024Updated 2 years ago
- FPGA demo for Digilent NEXYS 4 board☆22Oct 2, 2019Updated 6 years ago
- RISC-V CPU Core☆425Jun 24, 2025Updated 10 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- educational microarchitectures for risc-v isa☆747Sep 1, 2025Updated 7 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,906Apr 23, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆978Nov 15, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,142Mar 11, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,125Feb 11, 2026Updated 2 months ago
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,121Jun 27, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,221Apr 17, 2026Updated last week
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A directory of Western Digital’s RISC-V SweRV Cores☆881Mar 26, 2020Updated 6 years ago
- RISC-V Formal Verification Framework☆629Apr 6, 2022Updated 4 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- Chisel: A Modern Hardware Design Language☆4,644Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆687Jul 16, 2025Updated 9 months ago
- Support for Rocket Chip on Zynq FPGAs☆422Jan 29, 2019Updated 7 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 8 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,859Apr 14, 2026Updated 2 weeks ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆102Nov 22, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- RISC-V Tools (ISA Simulator and Tests)☆1,192Dec 22, 2022Updated 3 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- ☆111Oct 19, 2018Updated 7 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,010Mar 9, 2026Updated last month
- ☆246Nov 30, 2016Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- VeeR EH1 core☆935May 29, 2023Updated 2 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆419Updated this week
- chisel tutorial exercises and answers☆751Jan 6, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Documentation for the BOOM processor☆47Mar 8, 2017Updated 9 years ago
- GPGPU microprocessor architecture☆2,188Nov 8, 2024Updated last year
- RTL, Cmodel, and testbench for NVDLA☆2,061Mar 2, 2022Updated 4 years ago
- RISC-V Linux Port☆607Apr 12, 2019Updated 7 years ago
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- ☆33Oct 4, 2017Updated 8 years ago
- OpenTitan: Open source silicon root of trust☆3,328Updated this week