ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
☆1,763Updated this week
Alternatives and similar repositories for chipyard:
Users that are interested in chipyard are comparing it to the libraries listed below
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,826Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,013Updated 5 months ago
- 32-bit Superscalar RISC-V CPU☆948Updated 3 years ago
- Digital Design with Chisel☆810Updated 3 weeks ago
- VeeR EH1 core☆852Updated last year
- educational microarchitectures for risc-v isa☆701Updated 6 months ago
- Random instruction generator for RISC-V processor verification☆1,069Updated 3 weeks ago
- chisel tutorial exercises and answers☆712Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,478Updated this week
- Rocket Chip Generator☆3,365Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,019Updated 2 weeks ago
- OpenXuantie - OpenC910 Core☆1,225Updated 8 months ago
- A template project for beginning new Chisel work☆619Updated last month
- Flexible Intermediate Representation for RTL☆738Updated 6 months ago
- Scala based HDL☆1,732Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆911Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆564Updated 6 months ago
- RISC-V Cores, SoC platforms and SoCs☆861Updated 3 years ago
- ☆943Updated this week
- RISC-V CPU Core (RV32IM)☆1,374Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,216Updated this week
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,392Updated this week
- RISC-V Tools (ISA Simulator and Tests)☆1,154Updated 2 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆908Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆899Updated 3 months ago
- The OpenPiton Platform☆669Updated 4 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,679Updated 2 weeks ago
- The Ultra-Low Power RISC-V Core☆1,418Updated 4 months ago
- An open-source static random access memory (SRAM) compiler.☆875Updated 3 months ago
- A small, light weight, RISC CPU soft core☆1,363Updated 3 weeks ago