An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
☆2,183Mar 17, 2026Updated this week
Alternatives and similar repositories for chipyard
Users that are interested in chipyard are comparing it to the libraries listed below
Sorting:
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- Berkeley's Spatial Array Generator☆1,251Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,105Mar 11, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,611Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,001Mar 9, 2026Updated last week
- A template project for beginning new Chisel work☆694Feb 24, 2026Updated 3 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,121Sep 10, 2024Updated last year
- Digital Design with Chisel☆899Mar 13, 2026Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆314Mar 6, 2026Updated 2 weeks ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,845Mar 10, 2026Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- chisel tutorial exercises and answers☆748Jan 6, 2022Updated 4 years ago
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆164Jan 25, 2024Updated 2 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- Open-source high-performance RISC-V processor☆6,904Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,804Feb 17, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Mar 14, 2026Updated last week
- Spike, a RISC-V ISA Simulator☆3,045Updated this week
- ☆368Sep 12, 2025Updated 6 months ago
- Random instruction generator for RISC-V processor verification☆1,262Mar 5, 2026Updated 2 weeks ago
- Circuit IR Compilers and Tools☆2,065Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,063Feb 11, 2026Updated last month
- The OpenPiton Platform☆777Feb 25, 2026Updated 3 weeks ago
- Verilator open-source SystemVerilog simulator and lint system☆3,439Updated this week
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- ☆1,939Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,031Mar 2, 2022Updated 4 years ago
- The official repository for the gem5 computer-system architecture simulator.☆2,514Mar 13, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆878Updated this week
- VeeR EH1 core☆930May 29, 2023Updated 2 years ago
- Yosys Open SYnthesis Suite☆4,348Updated this week
- Scala based HDL☆1,935Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- Chisel examples and code snippets☆271Aug 1, 2022Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 4 months ago