Alternatives and similar repositories for chipyard

Users that are interested in chipyard are comparing it to the libraries listed below

• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,934Updated 2 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,050Updated 10 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,581Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,053Updated 3 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,090Updated last month
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,496Updated 3 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,288Updated last year
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆845Updated 2 weeks ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆893Updated 4 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• riscv-software-src / riscv-tests
  ☆1,033Updated last month
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,489Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆716Updated 4 months ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,543Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆716Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,321Updated this week
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆652Updated last month
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆971Updated 2 weeks ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆945Updated 3 weeks ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆924Updated 8 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆584Updated 11 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,540Updated 9 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated 10 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆711Updated 2 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,817Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆503Updated 7 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,819Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,611Updated last month