An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
☆2,335Jul 17, 2026Updated this week
Alternatives and similar repositories for chipyard
Users that are interested in chipyard are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rocket Chip Generator☆3,820Jun 2, 2026Updated last month
- Berkeley's Spatial Array Generator☆1,402Jun 30, 2026Updated 3 weeks ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,199Updated this week
- Chisel: A Modern Hardware Design Language☆4,729Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,028Jun 26, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A template project for beginning new Chisel work☆704Feb 24, 2026Updated 4 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,142Sep 10, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,024Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆324Jul 13, 2026Updated last week
- Open-source high-performance RISC-V processor☆7,149Updated this week
- educational microarchitectures for risc-v isa☆752Sep 1, 2025Updated 10 months ago
- Digital Design with Chisel☆923Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆616Aug 9, 2024Updated last year
- chisel tutorial exercises and answers☆755Jan 6, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆165Jan 25, 2024Updated 2 years ago
- ☆386Jun 14, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,976Jul 14, 2026Updated last week
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆531Jun 8, 2026Updated last month
- Spike, a RISC-V ISA Simulator☆3,177Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- Source files for SiFive's Freedom platforms☆1,145Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Circuit IR Compilers and Tools☆2,199Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,121Mar 2, 2022Updated 4 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,754Updated this week
- The OpenPiton Platform☆802Feb 25, 2026Updated 4 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,719Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,196Feb 11, 2026Updated 5 months ago
- Random instruction generator for RISC-V processor verification☆1,325Apr 3, 2026Updated 3 months ago
- ☆2,162Updated this week
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,267Jun 27, 2024Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,266May 29, 2026Updated last month
- Scala based HDL☆2,020Updated this week
- VeeR EH1 core☆955Updated this week
- Yosys Open SYnthesis Suite☆4,612Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,625Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆931Jul 8, 2026Updated last week