Alternatives and similar repositories for chipyard:

Users that are interested in chipyard are comparing it to the libraries listed below

• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,792Updated 3 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,001Updated 4 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,453Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,004Updated 6 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆800Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆708Updated 3 years ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,328Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆698Updated 5 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆840Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,057Updated 5 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆926Updated 3 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆736Updated 5 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,196Updated 7 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆558Updated 5 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆611Updated this week
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆901Updated 2 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,337Updated 3 years ago
• riscv-software-src / riscv-tests
  ☆928Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆856Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆893Updated 2 months ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,351Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆663Updated 3 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,719Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,152Updated 2 years ago
• sifive / freedom
  Source files for SiFive's Freedom platforms
  ☆1,113Updated 3 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆651Updated last week
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆860Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,188Updated last week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆637Updated 2 months ago
• riscv-non-isa / riscv-arch-test
  ☆534Updated last week