Alternatives and similar repositories for swerv-ISS:

Users that are interested in swerv-ISS are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH2
  ☆232Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆225Updated 5 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆863Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆182Updated this week
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆165Updated 9 years ago
• chipsalliance / VeeR-ISS
  ☆131Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆271Updated 8 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆177Updated 4 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 9 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆322Updated 3 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 5 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆365Updated last year
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆66Updated 5 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆156Updated last month
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆80Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆190Updated 9 months ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆151Updated 7 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆151Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆229Updated 5 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆208Updated 2 weeks ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated this week
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆124Updated 4 years ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆210Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆299Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆97Updated 3 years ago