Alternatives and similar repositories for swerv-ISS

Users that are interested in swerv-ISS are comparing it to the libraries listed below

• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆66Updated 6 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆876Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆250Updated 2 years ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆242Updated 6 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆328Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated last year
• openpower-cores / a2i
  ☆247Updated 3 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆174Updated 10 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 11 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 6 months ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆198Updated 2 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆216Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆171Updated 5 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆158Updated 7 years ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆319Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆165Updated 5 years ago
• cornell-brg / pymtl
  Python-based hardware modeling framework
  ☆245Updated 6 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆151Updated 3 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆396Updated 5 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• openpower-cores / a2o
  ☆142Updated 3 years ago
• embench / embench-iot
  The main Embench repository
  ☆298Updated last year
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆412Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 8 months ago