☆258Dec 22, 2022Updated 3 years ago
Alternatives and similar repositories for Cores-VeeR-EH2
Users that are interested in Cores-VeeR-EH2 are comparing it to the libraries listed below
Sorting:
- VeeR EL2 Core☆321Updated this week
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆495Nov 27, 2025Updated 3 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,257Oct 1, 2025Updated 5 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆225Jan 11, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Dec 10, 2019Updated 6 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆259Nov 6, 2024Updated last year
- The OpenPiton Platform☆774Feb 25, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆964Nov 15, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,785Feb 17, 2026Updated 2 weeks ago
- ☆152Oct 6, 2023Updated 2 years ago
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- ☆309Jan 23, 2026Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,153Feb 21, 2026Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆297Feb 4, 2026Updated last month
- ☆148Feb 29, 2024Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- OmniXtend cache coherence protocol☆82Jun 10, 2025Updated 8 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184May 8, 2025Updated 10 months ago
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆50Aug 24, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆659Updated this week
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 5 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated 2 weeks ago
- OpenXuantie - OpenC910 Core☆1,391Jun 28, 2024Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- RISC-V Verification Interface☆142Jan 28, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆571Oct 21, 2025Updated 4 months ago
- CORE-V Family of RISC-V Cores☆332Feb 13, 2025Updated last year