openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
☆2,440Updated last week
Alternatives and similar repositories for cva6:
Users that are interested in cva6 are comparing it to the libraries listed below
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,865Updated 2 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,514Updated 3 weeks ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,732Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,430Updated 9 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,284Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,049Updated 2 months ago
- A small, light weight, RISC CPU soft core☆1,385Updated 2 months ago
- VeeR EH1 core☆869Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,822Updated this week
- RISC-V Cores, SoC platforms and SoCs☆871Updated 4 years ago
- Rocket Chip Generator☆3,416Updated last week
- The OpenPiton Platform☆697Updated last month
- SERV - The SErial RISC-V CPU☆1,564Updated last month
- Random instruction generator for RISC-V processor verification☆1,097Updated 2 months ago
- An open-source microcontroller system based on RISC-V☆947Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,069Updated last month
- A directory of Western Digital’s RISC-V SweRV Cores☆863Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆997Updated 3 years ago
- OpenXuantie - OpenC910 Core☆1,260Updated 9 months ago
- ☆982Updated last week
- educational microarchitectures for risc-v isa☆712Updated last month
- RISC-V CPU Core (RV32IM)☆1,422Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,027Updated 7 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,160Updated 2 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆920Updated 3 weeks ago
- chisel tutorial exercises and answers☆720Updated 3 years ago
- Spike, a RISC-V ISA Simulator☆2,665Updated this week
- Scala based HDL☆1,772Updated this week
- Digital Design with Chisel☆826Updated 2 weeks ago
- Flexible Intermediate Representation for RTL☆741Updated 8 months ago