Rocket Chip Generator
☆3,773Apr 21, 2026Updated last month
Alternatives and similar repositories for rocket-chip
Users that are interested in rocket-chip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,161Mar 11, 2026Updated 2 months ago
- Chisel: A Modern Hardware Design Language☆4,661Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,262Updated this week
- chisel tutorial exercises and answers☆752Jan 6, 2022Updated 4 years ago
- Flexible Intermediate Representation for RTL☆750Aug 20, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,133Sep 10, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- educational microarchitectures for risc-v isa☆748Sep 1, 2025Updated 8 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆610Aug 9, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,015Updated this week
- Support for Rocket Chip on Zynq FPGAs☆422Jan 29, 2019Updated 7 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,142Feb 11, 2026Updated 3 months ago
- Digital Design with Chisel☆915Apr 30, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A template project for beginning new Chisel work☆698Feb 24, 2026Updated 2 months ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,841Mar 24, 2021Updated 5 years ago
- Open-source high-performance RISC-V processor☆7,023Updated this week
- Spike, a RISC-V ISA Simulator☆3,115Updated this week
- The root repo for lowRISC project and FPGA demos.☆601Aug 3, 2023Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated 2 weeks ago
- VeeR EH1 core☆942May 29, 2023Updated 2 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,191Dec 22, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,622Updated this week
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- Berkeley's Spatial Array Generator☆1,317Mar 29, 2026Updated last month
- Random instruction generator for RISC-V processor verification☆1,298Apr 3, 2026Updated last month
- An open-source microcontroller system based on RISC-V☆1,032Feb 6, 2024Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,833Aug 6, 2025Updated 9 months ago
- GNU toolchain for RISC-V, including GCC☆4,496Updated this week
- Scala based HDL☆1,988May 9, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Yosys Open SYnthesis Suite☆4,443May 15, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,085Mar 2, 2022Updated 4 years ago
- RISC-V SoC designed by students in UCAS☆1,527Apr 28, 2026Updated 3 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,553May 12, 2026Updated last week
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- OpenXuantie - OpenC910 Core☆1,433Jun 28, 2024Updated last year
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆235Aug 19, 2024Updated last year