chipsalliance / rocket-chipLinks
Rocket Chip Generator
☆3,543Updated last week
Alternatives and similar repositories for rocket-chip
Users that are interested in rocket-chip are comparing it to the libraries listed below
Sorting:
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,969Updated 4 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,959Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,611Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,872Updated 2 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- Chisel: A Modern Hardware Design Language☆4,393Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated 2 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,066Updated last year
- Scala based HDL☆1,847Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,667Updated last year
- chisel tutorial exercises and answers☆736Updated 3 years ago
- Spike, a RISC-V ISA Simulator☆2,823Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,403Updated last month
- RISC-V CPU Core (RV32IM)☆1,537Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,166Updated 3 months ago
- educational microarchitectures for risc-v isa☆719Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,117Updated 3 months ago
- RISC-V Cores, SoC platforms and SoCs☆896Updated 4 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,762Updated 4 years ago
- The Ultra-Low Power RISC-V Core☆1,598Updated last month
- OpenXuantie - OpenC910 Core☆1,314Updated last year
- ☆1,053Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,091Updated 3 years ago
- Digital Design with Chisel☆859Updated this week
- VeeR EH1 core☆894Updated 2 years ago
- Flexible Intermediate Representation for RTL☆747Updated last year
- An open-source microcontroller system based on RISC-V☆974Updated last year
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,054Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆962Updated 2 months ago