Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,850Mar 24, 2021Updated 5 years ago
Alternatives and similar repositories for e200_opensource
Users that are interested in e200_opensource are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Ultra-Low Power RISC-V Core☆1,893Aug 6, 2025Updated last year
- IC design and development should be faster,simpler and more reliable☆2,006Dec 31, 2021Updated 4 years ago
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆116Mar 24, 2021Updated 5 years ago
- Rocket Chip Generator☆3,840Jun 2, 2026Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,309Jul 31, 2026Updated last week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,597May 12, 2026Updated 2 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,194Dec 22, 2022Updated 3 years ago
- Source files for SiFive's Freedom platforms☆1,145Jul 17, 2026Updated 3 weeks ago
- RISC-V SoC designed by students in UCAS☆1,542Jun 5, 2026Updated 2 months ago
- RTL, Cmodel, and testbench for NVDLA☆2,134Mar 2, 2022Updated 4 years ago
- Chisel: A Modern Hardware Design Language☆4,754Updated this week
- Open-source high-performance RISC-V processor☆7,182Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,218Feb 11, 2026Updated 5 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,213Jul 22, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- OpenXuantie - OpenC910 Core☆1,462Jun 28, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,060Updated this week
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,147Sep 10, 2024Updated last year
- Must-have verilog systemverilog modules☆2,006Mar 12, 2026Updated 4 months ago
- OpenSource HummingBird RISC-V Software Development Kit☆178Dec 5, 2023Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,763Sep 18, 2021Updated 4 years ago
- A very simple and easy to understand RISC-V core.☆1,507Nov 9, 2023Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An open-source microcontroller system based on RISC-V☆1,057Feb 6, 2024Updated 2 years ago
- Verilog AXI components for FPGA implementation☆2,109Feb 27, 2025Updated last year
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,004Jul 28, 2026Updated last week
- LicheeTang 蜂鸟E203 Core☆204Jul 10, 2019Updated 7 years ago
- 为推广RISC-V尽些薄力☆311Jun 22, 2023Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,350Jul 29, 2026Updated last week
- A small, light weight, RISC CPU soft core☆1,570Dec 8, 2025Updated 8 months ago
- RISC-V Cores, SoC platforms and SoCs☆927Mar 26, 2021Updated 5 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆992Nov 15, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,650Updated this week
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆381Jul 12, 2017Updated 9 years ago
- GNU toolchain for RISC-V, including GCC☆4,585Jul 15, 2026Updated 3 weeks ago
- Random instruction generator for RISC-V processor verification☆1,337Apr 3, 2026Updated 4 months ago
- AMBA bus lecture material☆547Jan 21, 2020Updated 6 years ago
- ☆126Jul 2, 2022Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,286Sep 18, 2021Updated 4 years ago