Alternatives and similar repositories for e200_opensource

Users that are interested in e200_opensource are comparing it to the libraries listed below

• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,508Updated 7 months ago
• XUANTIE-RV / wujian100_open
  IC design and development should be faster，simpler and more reliable
  ☆1,938Updated 3 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,170Updated 2 years ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,506Updated 11 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,036Updated 8 months ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,900Updated 3 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,462Updated 3 years ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,786Updated last month
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,451Updated this week
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,274Updated 11 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,724Updated 3 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,860Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,328Updated last week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆881Updated 4 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆957Updated last month
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,247Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,775Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,547Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,126Updated 3 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆728Updated 3 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated last week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,794Updated this week
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• nvdla / hw
  RTL, Cmodel, and testbench for NVDLA
  ☆1,882Updated 3 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,024Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆878Updated 2 years ago
• riscv-software-src / riscv-tests
  ☆1,014Updated last month
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆837Updated 3 weeks ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,312Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,286Updated last week