Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,814Mar 24, 2021Updated 4 years ago
Alternatives and similar repositories for e200_opensource
Users that are interested in e200_opensource are comparing it to the libraries listed below
Sorting:
- The Ultra-Low Power RISC-V Core☆1,738Aug 6, 2025Updated 6 months ago
- IC design and development should be faster,simpler and more reliable☆1,985Dec 31, 2021Updated 4 years ago
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆115Mar 24, 2021Updated 4 years ago
- Rocket Chip Generator☆3,685Feb 17, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,966Jun 27, 2024Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,493Jan 7, 2026Updated last month
- RISC-V Tools (ISA Simulator and Tests)☆1,176Dec 22, 2022Updated 3 years ago
- RISC-V SoC designed by students in UCAS☆1,508Jan 14, 2026Updated last month
- RTL, Cmodel, and testbench for NVDLA☆2,025Mar 2, 2022Updated 3 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,026Feb 11, 2026Updated 2 weeks ago
- Chisel: A Modern Hardware Design Language☆4,588Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,817Feb 18, 2026Updated last week
- VeeR EH1 core☆927May 29, 2023Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,079Feb 5, 2026Updated 3 weeks ago
- Open-source high-performance RISC-V processor☆6,875Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,187May 26, 2025Updated 9 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,108Sep 10, 2024Updated last year
- Must-have verilog systemverilog modules☆1,929Feb 19, 2026Updated last week
- RISC-V CPU Core (RV32IM)