SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,633Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for e200_opensource
- The Ultra-Low Power RISC-V Core☆1,287Updated last month
- RISC-V Tools (ISA Simulator and Tests)☆1,144Updated last year
- Must-have verilog systemverilog modules☆1,657Updated 2 weeks ago
- RISC-V CPU Core (RV32IM)☆1,278Updated 3 years ago
- Rocket Chip Generator☆3,266Updated last week
- IC design and development should be faster,simpler and more reliable☆1,873Updated 2 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,160Updated 4 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,749Updated last month
- RISC-V SoC designed by students in UCAS☆1,399Updated 2 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆981Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,515Updated last week
- RISC-V Cores, SoC platforms and SoCs☆841Updated 3 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,126Updated last week
- OpenXuantie - OpenC910 Core☆1,168Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,521Updated 11 months ago
- A very simple and easy to understand RISC-V core.☆1,111Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,658Updated this week
- Verilog library for ASIC and FPGA designers☆1,195Updated 6 months ago
- A small, light weight, RISC CPU soft core☆1,305Updated last month
- 32-bit Superscalar RISC-V CPU☆868Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆965Updated 4 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆852Updated 2 weeks ago
- Scala based HDL☆1,673Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,382Updated this week
- 关于RISC-V你所需要知道的一切☆542Updated last year
- Digital Design with Chisel☆771Updated 2 weeks ago
- Random instruction generator for RISC-V processor verification☆1,027Updated 2 months ago
- chisel tutorial exercises and answers☆696Updated 2 years ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,291Updated this week
- educational microarchitectures for risc-v isa☆688Updated 3 months ago