SI-RISCV / e200_opensourceLinks
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,768Updated 4 years ago
Alternatives and similar repositories for e200_opensource
Users that are interested in e200_opensource are comparing it to the libraries listed below
Sorting:
- The Ultra-Low Power RISC-V Core☆1,617Updated 2 months ago
- IC design and development should be faster,simpler and more reliable☆1,972Updated 3 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,167Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,326Updated last year
- Rocket Chip Generator☆3,566Updated last month
- RISC-V CPU Core (RV32IM)☆1,547Updated 4 years ago
- Must-have verilog systemverilog modules☆1,843Updated 2 months ago
- RISC-V SoC designed by students in UCAS☆1,482Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,703Updated last year
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆994Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,979Updated 5 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,068Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,981Updated last week
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,175Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,886Updated 3 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,416Updated 2 months ago
- RTL, Cmodel, and testbench for NVDLA☆1,941Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,123Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,822Updated 7 months ago
- chisel tutorial exercises and answers☆735Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,100Updated 4 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,635Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,382Updated last week
- Documentation for XiangShan☆426Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,628Updated this week
- Verilog PCI express components☆1,435Updated last year
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- 关于RISC-V你所需要知道的一切☆561Updated 2 years ago
- Digital Design with Chisel☆861Updated this week