SI-RISCV / e200_opensourceLinks
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,751Updated 4 years ago
Alternatives and similar repositories for e200_opensource
Users that are interested in e200_opensource are comparing it to the libraries listed below
Sorting:
- The Ultra-Low Power RISC-V Core☆1,552Updated this week
- IC design and development should be faster,simpler and more reliable☆1,966Updated 3 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- Rocket Chip Generator☆3,503Updated 2 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,056Updated 10 months ago
- Must-have verilog systemverilog modules☆1,816Updated this week
- RISC-V CPU Core (RV32IM)☆1,510Updated 3 years ago
- RISC-V SoC designed by students in UCAS☆1,471Updated this week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆979Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,922Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,609Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,949Updated 3 months ago
- Verilog AXI components for FPGA implementation☆1,783Updated 5 months ago
- OpenXuantie - OpenC910 Core☆1,296Updated last year
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,842Updated last month
- Random instruction generator for RISC-V processor verification☆1,146Updated 2 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,378Updated 3 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,571Updated this week
- Scala based HDL☆1,833Updated this week
- chisel tutorial exercises and answers☆736Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,069Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,600Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,101Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,343Updated this week
- A small, light weight, RISC CPU soft core☆1,439Updated 6 months ago
- educational microarchitectures for risc-v isa☆718Updated 4 months ago
- RTL, Cmodel, and testbench for NVDLA☆1,916Updated 3 years ago
- Digital Design with Chisel☆852Updated last month
- Verilog PCI express components☆1,396Updated last year