SI-RISCV / e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
☆2,686Updated 4 years ago
Alternatives and similar repositories for e200_opensource:
Users that are interested in e200_opensource are comparing it to the libraries listed below
- The Ultra-Low Power RISC-V Core☆1,441Updated 5 months ago
- IC design and development should be faster,simpler and more reliable☆1,915Updated 3 years ago
- Must-have verilog systemverilog modules☆1,744Updated 4 months ago
- RISC-V CPU Core (RV32IM)☆1,398Updated 3 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,158Updated 2 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆920Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,847Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,247Updated this week
- Verilog AXI components for FPGA implementation☆1,655Updated 3 weeks ago
- OpenXuantie - OpenC910 Core☆1,237Updated 8 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,370Updated 8 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,016Updated 6 months ago
- Rocket Chip Generator☆3,383Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,699Updated last month
- RISC-V Cores, SoC platforms and SoCs☆867Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆972Updated 3 years ago
- 为推广RISC-V尽些薄力☆311Updated last year
- 关于RISC-V你所需要知道的一切☆552Updated last year
- Verilog PCI express components☆1,252Updated 10 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,028Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,240Updated this week
- Random instruction generator for RISC-V processor verification☆1,080Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,494Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,792Updated this week
- RISC-V SoC designed by students in UCAS☆1,442Updated 2 months ago
- Documentation for XiangShan☆408Updated last week
- 中文版 Parallel Programming for FPGAs☆719Updated 7 months ago
- VeeR EH1 core☆862Updated last year
- A small, light weight, RISC CPU soft core☆1,368Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆904Updated 4 months ago