westerndigitalcorporation / swerv_eh1_fpgaLinks
FPGA reference design for the the Swerv EH1 Core
☆72Updated 5 years ago
Alternatives and similar repositories for swerv_eh1_fpga
Users that are interested in swerv_eh1_fpga are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆121Updated this week
- Yet Another RISC-V Implementation☆98Updated last year
- pulp_soc is the core building component of PULP based SoCs☆81Updated 7 months ago
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Naive Educational RISC V processor☆90Updated 2 weeks ago
- ☆32Updated 2 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- PCI Express controller model☆68Updated 3 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆115Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- ☆60Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- RISC-V Nexus Trace TG documentation and reference code☆53Updated 9 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated last week
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆107Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Clarvi simple RISC-V processor for teaching☆58Updated 8 years ago