westerndigitalcorporation / swerv_eh1_fpgaLinks
FPGA reference design for the the Swerv EH1 Core
☆72Updated 6 years ago
Alternatives and similar repositories for swerv_eh1_fpga
Users that are interested in swerv_eh1_fpga are comparing it to the libraries listed below
Sorting:
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆120Updated 4 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 9 months ago
- FuseSoC standard core library☆151Updated 2 weeks ago
- Naive Educational RISC V processor☆93Updated 2 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- ☆33Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆110Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago
- Clarvi simple RISC-V processor for teaching☆58Updated 8 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆106Updated 4 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- ☆60Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- PCI Express controller model☆71Updated 3 years ago