chipsalliance / omnixtend
OmniXtend cache coherence protocol
☆79Updated 4 years ago
Alternatives and similar repositories for omnixtend:
Users that are interested in omnixtend are comparing it to the libraries listed below
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 8 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆89Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆89Updated last week
- Provides various testers for chisel users☆100Updated 2 years ago
- ☆83Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 10 months ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Virtio implementation in SystemVerilog☆47Updated 7 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 11 months ago
- ☆46Updated 2 weeks ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆17Updated 10 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆35Updated 5 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆35Updated 3 years ago
- ☆92Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ☆86Updated 2 years ago
- ☆82Updated last month
- Advanced Interface Bus (AIB) die-to-die hardware open source☆134Updated 6 months ago