SonicBOOM: The Berkeley Out-of-Order Machine
☆2,217Aug 11, 2026Updated this week
Alternatives and similar repositories for riscv-boom
Users that are interested in riscv-boom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rocket Chip Generator☆3,843Jun 2, 2026Updated 2 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,355Jul 29, 2026Updated 2 weeks ago
- Chisel: A Modern Hardware Design Language☆4,758Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,064Updated this week
- educational microarchitectures for risc-v isa☆753Sep 1, 2025Updated 11 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Open-source high-performance RISC-V processor☆7,191Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,032Jun 26, 2026Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,190Jul 15, 2026Updated last month
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,149Sep 10, 2024Updated last year
- OpenXuantie - OpenC910 Core☆1,463Jun 28, 2024Updated 2 years ago
- Spike, a RISC-V ISA Simulator☆3,197Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,221Feb 11, 2026Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Digital Design with Chisel☆926Jul 21, 2026Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,333Jul 31, 2026Updated 2 weeks ago
- chisel tutorial exercises and answers☆757Jan 6, 2022Updated 4 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- ☆389Jun 14, 2026Updated 2 months ago
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,010Updated this week
- Source files for SiFive's Freedom platforms☆1,145Jul 17, 2026Updated 3 weeks ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆381Jul 12, 2017Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- 32-bit Superscalar RISC-V CPU☆1,289Sep 18, 2021Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,342Apr 3, 2026Updated 4 months ago
- ☆1,229Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,845Updated this week
- ☆2,205Aug 5, 2026Updated last week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆261Updated this week
- A template project for beginning new Chisel work☆707Feb 24, 2026Updated 5 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,754Updated this week
- RISC-V SoC designed by students in UCAS☆1,542Jun 5, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VeeR EH2 core☆275Jul 20, 2026Updated 3 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆937Updated this week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,850Mar 24, 2021Updated 5 years ago
- A Linux-capable RISC-V multicore for and by the world☆825Jul 13, 2026Updated last month
- RISC-V Tools (ISA Simulator and Tests)☆1,194Dec 22, 2022Updated 3 years ago
- Berkeley's Spatial Array Generator☆1,427Jun 30, 2026Updated last month
- The OpenPiton Platform☆809Feb 25, 2026Updated 5 months ago