pulp-platform / axiLinks
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
☆1,377Updated last week
Alternatives and similar repositories for axi
Users that are interested in axi are comparing it to the libraries listed below
Sorting:
- Verilog AXI components for FPGA implementation☆1,822Updated 7 months ago
- Common SystemVerilog components☆660Updated last week
- Verilog AXI stream components for FPGA implementation☆831Updated 7 months ago
- Verilog PCI express components☆1,435Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,121Updated 4 months ago
- Random instruction generator for RISC-V processor verification☆1,171Updated 3 months ago
- Various HDL (Verilog) IP Cores☆835Updated 4 years ago
- VeeR EH1 core☆898Updated 2 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆594Updated 7 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆599Updated last week
- 32-bit Superscalar RISC-V CPU☆1,100Updated 4 years ago
- Bus bridges and other odds and ends☆589Updated 5 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,635Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆571Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆607Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆513Updated 10 months ago
- Verilog I2C interface for FPGA implementation☆644Updated 7 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆516Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆674Updated 2 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆440Updated 4 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆935Updated 10 months ago
- Verilog UART☆506Updated 7 months ago
- AMBA bus lecture material☆467Updated 5 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- The RIFFA development repository☆849Updated last year
- SystemVerilog to Verilog conversion☆668Updated 3 months ago
- lowRISC Style Guides☆457Updated 3 months ago
- The UVM written in Python☆452Updated last week
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- cocotb: Python-based chip (RTL) verification☆2,102Updated this week