pulp-platform / axiLinks
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
☆1,453Updated last month
Alternatives and similar repositories for axi
Users that are interested in axi are comparing it to the libraries listed below
Sorting:
- Verilog AXI components for FPGA implementation☆1,919Updated 10 months ago
- Common SystemVerilog components☆694Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,158Updated 7 months ago
- Verilog PCI express components☆1,505Updated last year
- Verilog AXI stream components for FPGA implementation☆852Updated 10 months ago
- Random instruction generator for RISC-V processor verification☆1,236Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,169Updated 4 years ago
- Various HDL (Verilog) IP Cores☆859Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆636Updated this week
- Bus bridges and other odds and ends☆618Updated 8 months ago
- VeeR EH1 core☆918Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆632Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,728Updated 3 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆451Updated 7 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆533Updated last year
- synthesiseable ieee 754 floating point library in verilog☆708Updated 2 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆606Updated 7 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆951Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆557Updated 2 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆591Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆410Updated 3 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆545Updated 4 years ago
- AMBA bus lecture material☆497Updated 5 years ago
- cocotb: Python-based chip (RTL) verification☆2,210Updated last week
- The UVM written in Python☆491Updated 2 weeks ago
- Verilog I2C interface for FPGA implementation☆669Updated 10 months ago
- Verilog UART☆523Updated 10 months ago
- training labs and examples☆443Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,385Updated last year
- SystemVerilog to Verilog conversion☆693Updated last month