Alternatives and similar repositories for darkriscv

Users that are interested in darkriscv are comparing it to the libraries listed below

• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,485Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,947Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,727Updated last week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,830Updated last year
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,031Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,707Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,704Updated 2 weeks ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,596Updated 4 years ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,640Updated 3 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,147Updated 4 years ago
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,930Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,152Updated 6 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,893Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆906Updated 4 years ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆994Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆914Updated 2 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,171Updated 2 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,376Updated last year
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,136Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,218Updated 2 months ago
• riscv-software-src / riscv-tests
  ☆1,092Updated 2 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,069Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,185Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆678Updated 5 months ago
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,634Updated last week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,028Updated 2 weeks ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,672Updated 4 months ago
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,162Updated last year
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,093Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,373Updated last week