Alternatives and similar repositories for ibex

Users that are interested in ibex are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,248Updated 4 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆922Updated 2 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆908Updated 4 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆960Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆758Updated 3 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,791Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,128Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆763Updated 4 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,067Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,745Updated last month
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,633Updated 4 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,504Updated last month
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,384Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,999Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆653Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,248Updated this week
• riscv-software-src / riscv-tests
  ☆1,117Updated 2 weeks ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,387Updated last year
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• riscv-non-isa / riscv-arch-test
  ☆647Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆1,000Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆704Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆623Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆893Updated 2 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆699Updated 2 months ago