lowRISC / ibexLinks
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
☆1,547Updated 2 weeks ago
Alternatives and similar repositories for ibex
Users that are interested in ibex are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,077Updated this week
- VeeR EH1 core☆878Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,126Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,024Updated 3 years ago
- RISC-V Cores, SoC platforms and SoCs☆881Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,286Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆914Updated 6 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 6 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,293Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,775Updated last month
- RISC-V CPU Core (RV32IM)☆1,462Updated 3 years ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,487Updated this week
- SERV - The SErial RISC-V CPU☆1,589Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆701Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,860Updated this week
- Common SystemVerilog components☆620Updated 3 weeks ago
- Verilog library for ASIC and FPGA designers☆1,289Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆545Updated last week
- A small, light weight, RISC CPU soft core☆1,409Updated 3 months ago
- educational microarchitectures for risc-v isa☆714Updated 2 months ago
- ☆1,011Updated last month
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,900Updated 3 weeks ago
- Digital Design with Chisel☆837Updated 3 weeks ago
- Scala based HDL☆1,794Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,506Updated 11 months ago
- Linux on LiteX-VexRiscv☆636Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆630Updated last week
- A directory of Western Digital’s RISC-V SweRV Cores☆866Updated 5 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated 2 weeks ago