Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)
☆2,004Jul 28, 2026Updated last week
Alternatives and similar repositories for ibex
Users that are interested in ibex are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,060Updated this week
- OpenTitan: Open source silicon root of trust☆3,581Updated this week
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,309Jul 31, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Random instruction generator for RISC-V processor verification☆1,337Apr 3, 2026Updated 4 months ago
- SERV - The SErial RISC-V CPU☆1,852Jul 10, 2026Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆992Nov 15, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,218Feb 11, 2026Updated 5 months ago
- Rocket Chip Generator☆3,840Jun 2, 2026Updated 2 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆709Jul 17, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,650Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,446Updated this week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆566Nov 26, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Common SystemVerilog components☆777Jul 29, 2026Updated last week
- An open-source microcontroller system based on RISC-V☆1,057Feb 6, 2024Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,286Sep 18, 2021Updated 4 years ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- A demo system for Ibex including debug support and some peripherals☆98Jul 16, 2026Updated 3 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆493May 8, 2026Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,213Jul 22, 2026Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,350Jul 29, 2026Updated last week
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Verilator open-source SystemVerilog simulator and lint system☆3,826Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,597May 12, 2026Updated 2 months ago
- VeeR EL2 Core☆343Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆677Jul 7, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆630Jul 24, 2026Updated 2 weeks ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,221Updated this week
- A Linux-capable RISC-V multicore for and by the world☆824Jul 13, 2026Updated 3 weeks ago
- cocotb: Python-based chip (RTL) verification☆2,470Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,892Mar 25, 2026Updated 4 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Yosys Open SYnthesis Suite☆4,656Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,188Jul 15, 2026Updated 3 weeks ago
- An abstraction library for interfacing EDA tools☆784Updated this week
- RISC-V Cores, SoC platforms and SoCs☆927Mar 26, 2021Updated 5 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆277Nov 6, 2024Updated last year
- RISC-V CPU Core (RV32IM)☆1,763Sep 18, 2021Updated 4 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,904Updated this week