lowRISC / ibexLinks
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
☆1,646Updated last month
Alternatives and similar repositories for ibex
Users that are interested in ibex are comparing it to the libraries listed below
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,122Updated 4 months ago
- Random instruction generator for RISC-V processor verification☆1,177Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,106Updated 4 years ago
- VeeR EH1 core☆900Updated 2 years ago
- RISC-V Cores, SoC platforms and SoCs☆897Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,385Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆936Updated 11 months ago
- A Linux-capable RISC-V multicore for and by the world☆741Updated 2 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆673Updated 3 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,999Updated last week
- The OpenPiton Platform☆732Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,659Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,344Updated last week
- RISC-V CPU Core (RV32IM)☆1,554Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,117Updated this week
- A small, light weight, RISC CPU soft core☆1,465Updated 2 months ago
- OpenXuantie - OpenC910 Core☆1,331Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,638Updated last week
- Common SystemVerilog components☆665Updated 3 weeks ago
- Verilog library for ASIC and FPGA designers☆1,341Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,981Updated 5 months ago
- An Open-source FPGA IP Generator☆1,011Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆602Updated this week
- ☆1,069Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆515Updated 10 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,892Updated 3 months ago
- An open-source static random access memory (SRAM) compiler.☆956Updated this week
- Digital Design with Chisel☆863Updated this week
- A directory of Western Digital’s RISC-V SweRV Cores☆872Updated 5 years ago
- RISC-V Formal Verification Framework☆610Updated 3 years ago