pulp-platform / pulp_socLinks
pulp_soc is the core building component of PULP based SoCs
☆81Updated 7 months ago
Alternatives and similar repositories for pulp_soc
Users that are interested in pulp_soc are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- Generic Register Interface (contains various adapters)☆130Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- RISC-V Verification Interface☆107Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆84Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 11 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆115Updated 4 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated 3 weeks ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- 64-bit multicore Linux-capable RISC-V processor☆97Updated 5 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 11 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year