pulp-platform / pulp_socLinks
pulp_soc is the core building component of PULP based SoCs
☆81Updated 10 months ago
Alternatives and similar repositories for pulp_soc
Users that are interested in pulp_soc are comparing it to the libraries listed below
Sorting:
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- Generic Register Interface (contains various adapters)☆134Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆76Updated last month
- Simple runtime for Pulp platforms☆50Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆190Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- RISC-V System on Chip Template☆160Updated 4 months ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- RISC-V Verification Interface☆136Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆144Updated this week
- Platform Level Interrupt Controller☆43Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- FPGA tool performance profiling☆104Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆134Updated this week
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆145Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago