Alternatives and similar repositories for pulp_soc

Users that are interested in pulp_soc are comparing it to the libraries listed below

• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆76Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆70Updated last week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆126Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆189Updated 2 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆179Updated 6 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆85Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 2 weeks ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆101Updated 7 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 3 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 9 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• riscv / riscv-test-env
  ☆50Updated 2 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 11 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆246Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆69Updated 4 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆125Updated this week