pulp-platform / pulp_soc
pulp_soc is the core building component of PULP based SoCs
☆79Updated last month
Alternatives and similar repositories for pulp_soc:
Users that are interested in pulp_soc are comparing it to the libraries listed below
- Generic Register Interface (contains various adapters)☆116Updated 7 months ago
- The multi-core cluster of a PULP system.☆90Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆146Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- Simple runtime for Pulp platforms☆45Updated last month
- ☆92Updated last year
- RISC-V Verification Interface☆89Updated 2 months ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- An Open-Source Design and Verification Environment for RISC-V☆80Updated 4 years ago
- RISC-V System on Chip Template☆158Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- ☆55Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 5 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆54Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- ☆84Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week