riscvarchive / riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
☆870Updated 4 years ago
Alternatives and similar repositories for riscv-cores-list:
Users that are interested in riscv-cores-list are comparing it to the libraries listed below
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,045Updated 2 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,512Updated 2 weeks ago
- VeeR EH1 core☆867Updated last year
- Random instruction generator for RISC-V processor verification☆1,092Updated 2 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,161Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,812Updated this week
- 32-bit Superscalar RISC-V CPU☆989Updated 3 years ago
- ☆972Updated last week
- ☆552Updated 2 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆906Updated 5 months ago
- chisel tutorial exercises and answers☆720Updated 3 years ago
- educational microarchitectures for risc-v isa☆711Updated last month
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆649Updated 5 months ago
- A directory of Western Digital’s RISC-V SweRV Cores☆863Updated 5 years ago
- OpenXuantie - OpenC910 Core☆1,257Updated 9 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,862Updated last week
- The OpenPiton Platform☆695Updated last month
- Digital Design with Chisel☆824Updated last week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,027Updated 7 months ago
- Fork of OpenOCD that has RISC-V support☆473Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,252Updated last week
- Working Draft of the RISC-V Debug Specification Standard☆483Updated last month
- RISC-V CPU Core (RV32IM)☆1,417Updated 3 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆569Updated 8 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆490Updated 4 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,422Updated 9 months ago
- RISC-V Formal Verification Framework☆596Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆678Updated last month
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,438Updated this week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆929Updated this week