Alternatives and similar repositories for riscv-cores-list

Users that are interested in riscv-cores-list are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,168Updated 8 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆921Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,746Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,173Updated 4 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,246Updated 4 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,384Updated last year
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆959Updated last year
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,631Updated 4 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• riscv-software-src / riscv-tests
  ☆1,110Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆893Updated 2 months ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,174Updated 3 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆732Updated 4 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Updated last year
• riscv-non-isa / riscv-arch-test
  ☆641Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆763Updated 4 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,115Updated last week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,046Updated 2 weeks ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,107Updated last year
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆880Updated 5 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆536Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,477Updated last month
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆744Updated 4 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆622Updated 3 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,059Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆758Updated 2 weeks ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆504Updated last month
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆601Updated 2 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆651Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆700Updated last month