Alternatives and similar repositories for riscv-cores-list:

Users that are interested in riscv-cores-list are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,033Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆865Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,507Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,081Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆975Updated 3 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆709Updated 3 weeks ago
• riscv-software-src / riscv-tests
  ☆963Updated last month
• riscv-non-isa / riscv-arch-test
  ☆551Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆820Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,848Updated last week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,244Updated 9 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆565Updated 7 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,020Updated 6 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,403Updated 3 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆714Updated 3 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,800Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,242Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,516Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆595Updated 2 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆677Updated 3 weeks ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆863Updated 5 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,448Updated 5 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆883Updated 4 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆525Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆511Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,371Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago