Alternatives and similar repositories for sv-tests

Users that are interested in sv-tests are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆269Updated last month
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 10 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆489Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆458Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆474Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆483Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆628Updated last week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆308Updated 2 months ago
• svunit / svunit
  ☆207Updated 9 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆311Updated 5 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆688Updated last month
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 10 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆436Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆689Updated last week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆304Updated 2 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 2 months ago
• subbdue / systemverilog.io
  Code used in
  ☆199Updated 8 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆207Updated last year
• accellera-official / uvm-core
  ☆104Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated last month
• accellera / uvm
  ☆57Updated 9 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆338Updated 2 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆187Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 6 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆309Updated this week