Alternatives and similar repositories for sv-tests:

Users that are interested in sv-tests are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆388Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated 3 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆422Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆616Updated 2 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆606Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆189Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆436Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆277Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆250Updated 2 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆444Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆568Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆480Updated 2 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆291Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆130Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆419Updated 7 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆137Updated 2 months ago
• svunit / svunit
  ☆199Updated last month
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 6 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆381Updated 2 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆275Updated 5 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆177Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆519Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆175Updated 4 months ago
• raysalemi / Python4RTLVerification
  ☆154Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆254Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆313Updated last week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆729Updated this week
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆320Updated 2 weeks ago