Test suite designed to check compliance with the SystemVerilog standard.
☆390Aug 28, 2026Updated this week
Alternatives and similar repositories for sv-tests
Users that are interested in sv-tests are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆473Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- SystemVerilog compiler and language services☆1,124Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 2 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,924Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog to Verilog conversion☆749Aug 18, 2026Updated 2 weeks ago
- SystemVerilog synthesis tool☆236Mar 10, 2025Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,890Updated this week
- A Linux-capable RISC-V multicore for and by the world☆827Jul 13, 2026Updated last month
- An abstraction library for interfacing EDA tools☆790Aug 12, 2026Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆680Jul 7, 2026Updated last month
- SystemVerilog linter☆391Nov 6, 2025Updated 9 months ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆621Jan 3, 2026Updated 7 months ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- cocotb: Python-based chip (RTL) verification☆2,486Updated this week
- SystemVerilog language server☆584Aug 25, 2026Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆148Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆543Aug 5, 2026Updated 3 weeks ago
- The UVM written in Python☆568Updated this week
- ☆30Oct 2, 2023Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,453Aug 24, 2026Updated last week
- ☆136Aug 14, 2026Updated 2 weeks ago
- SystemVerilog design elaborator into word-level netlist form☆249Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- Code generation tool for control and status registers☆468Aug 16, 2026Updated 2 weeks ago
- Hardware Description Languages☆1,169Jul 9, 2026Updated last month
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- Mutation Cover with Yosys (MCY)☆97Aug 5, 2026Updated 3 weeks ago
- SystemVerilog grammar for tree-sitter☆123Nov 11, 2024Updated last year
- Common SystemVerilog components☆792Aug 21, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,675Updated this week
- high-performance RTL simulator☆195Aug 4, 2026Updated 3 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Yosys Open SYnthesis Suite☆4,727Updated this week
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,350Apr 3, 2026Updated 4 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,032Updated this week
- ☆99Jul 22, 2026Updated last month
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆240Updated this week