Alternatives and similar repositories for sv-tests

Users that are interested in sv-tests are comparing it to the libraries listed below

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated 3 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆631Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆438Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆251Updated 3 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆455Updated 3 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆281Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆194Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆391Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆500Updated 3 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆278Updated 2 weeks ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆297Updated 2 months ago
• svunit / svunit
  ☆201Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆429Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆563Updated last month
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 7 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆262Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆139Updated 3 months ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆208Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆757Updated this week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆135Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆121Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆186Updated 7 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆693Updated last month
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆277Updated last week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆254Updated 3 months ago