Alternatives and similar repositories for SuperScalar-RISCV-CPU

Users that are interested in SuperScalar-RISCV-CPU are comparing it to the libraries listed below

• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆136Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆265Updated last week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆129Updated 6 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆258Updated 3 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆151Updated last year
• subbdue / systemverilog.io
  Code used in
  ☆202Updated 8 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆316Updated last month
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆149Updated 9 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆193Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆187Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆212Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆145Updated 6 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆172Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆285Updated 5 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆292Updated this week
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆101Updated 5 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆264Updated 8 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆305Updated 2 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆101Updated 5 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆86Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆135Updated 7 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆153Updated 6 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆160Updated 5 months ago