risclite / SuperScalar-RISCV-CPULinks
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
☆214Updated 4 years ago
Alternatives and similar repositories for SuperScalar-RISCV-CPU
Users that are interested in SuperScalar-RISCV-CPU are comparing it to the libraries listed below
Sorting:
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- Verilog Configurable Cache☆178Updated 6 months ago
- Basic RISC-V Test SoC☆129Updated 6 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆157Updated this week
- Various caches written in Verilog-HDL☆124Updated 10 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 7 months ago
- Instruction Set Generator initially contributed by Futurewei☆288Updated last year
- VeeR EL2 Core☆286Updated 2 weeks ago
- RISC-V CPU Core☆337Updated 2 weeks ago
- Verilog implementation of a RISC-V core☆118Updated 6 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆258Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆211Updated this week
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Labs to learn SpinalHDL☆148Updated 11 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆504Updated 4 months ago
- ☆179Updated last year
- ☆238Updated 2 years ago
- SystemC/TLM-2.0 Co-simulation framework☆247Updated last month
- AMBA bus generator including AXI, AHB, and APB☆102Updated 3 years ago
- ☆163Updated last month
- IEEE 754 floating point unit in Verilog☆138Updated 9 years ago
- OpenXuantie - OpenE902 Core☆150Updated 11 months ago
- ☆289Updated 3 months ago
- AHB3-Lite Interconnect☆89Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 6 months ago