risclite / SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
☆199Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for SuperScalar-RISCV-CPU
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆123Updated 5 years ago
- Verilog Configurable Cache☆167Updated 2 months ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- Various caches written in Verilog-HDL☆113Updated 9 years ago
- RISC-V CPU Core☆288Updated 5 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆266Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆225Updated last week
- VeeR EL2 Core☆251Updated this week
- Vector processor for RISC-V vector ISA☆110Updated 4 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆291Updated 2 months ago
- OpenXuantie - OpenE906 Core☆137Updated 4 months ago
- IEEE 754 floating point unit in Verilog☆128Updated 8 years ago
- ☆215Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- Wrapper for Rocket-Chip on FPGAs☆125Updated 2 years ago
- OpenXuantie - OpenE902 Core☆137Updated 4 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆259Updated 4 years ago
- Opensource DDR3 Controller☆212Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆438Updated 3 weeks ago
- ☆269Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆264Updated 6 months ago
- Common SystemVerilog components☆518Updated this week
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 3 weeks ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆176Updated 2 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆158Updated 2 years ago