risclite / SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
☆199Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for SuperScalar-RISCV-CPU
- Verilog Configurable Cache☆167Updated 2 months ago
- An AXI4 crossbar implementation in SystemVerilog☆121Updated 5 months ago
- Various caches written in Verilog-HDL☆113Updated 9 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆122Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 4 months ago
- Instruction Set Generator initially contributed by Futurewei☆264Updated last year
- RISC-V CPU Core☆287Updated 5 months ago
- VeeR EL2 Core☆252Updated this week
- Vector processor for RISC-V vector ISA☆109Updated 4 years ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- ☆214Updated last year
- Wrapper for Rocket-Chip on FPGAs☆124Updated 2 years ago
- OpenXuantie - OpenE902 Core☆136Updated 4 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆172Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆433Updated 2 weeks ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆114Updated 4 years ago
- ☆160Updated 10 months ago
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- Common SystemVerilog components☆513Updated this week
- ☆269Updated last month
- RISC-V System on Chip Template☆153Updated this week
- AHB3-Lite Interconnect☆81Updated 5 months ago
- SystemC/TLM-2.0 Co-simulation framework☆222Updated 2 weeks ago
- Comment on the rocket-chip source code☆168Updated 6 years ago
- ☆61Updated 2 months ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆54Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆258Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆258Updated 6 months ago