risclite / SuperScalar-RISCV-CPULinks
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
☆218Updated 5 years ago
Alternatives and similar repositories for SuperScalar-RISCV-CPU
Users that are interested in SuperScalar-RISCV-CPU are comparing it to the libraries listed below
Sorting:
- Various caches written in Verilog-HDL☆126Updated 10 years ago
- Verilog Configurable Cache☆183Updated 10 months ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- SpinalHDL-tutorial based on Jupyter Notebook☆141Updated last year
- ☆244Updated 2 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated last year
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆273Updated last week
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Basic RISC-V Test SoC☆144Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- Code used in☆196Updated 8 years ago
- VeeR EL2 Core☆297Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆256Updated 4 months ago
- OpenXuantie - OpenE902 Core☆156Updated last year
- RISC-V Torture Test☆197Updated last year
- ☆297Updated last week
- Verilog implementation of a RISC-V core☆125Updated 6 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆105Updated last year
- ☆189Updated last year
- ☆195Updated 3 months ago
- ☆145Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 10 months ago
- Verilog UART☆182Updated 12 years ago
- Labs to learn SpinalHDL☆149Updated last year