SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
☆236Aug 25, 2020Updated 5 years ago
Alternatives and similar repositories for SuperScalar-RISCV-CPU
Users that are interested in SuperScalar-RISCV-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 32-bit Superscalar RISC-V CPU☆1,281Sep 18, 2021Updated 4 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,188Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆989Nov 15, 2024Updated last year
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆380Jul 12, 2017Updated 9 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆190Apr 4, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆18Updated this week
- Vector processor for RISC-V vector ISA☆141Oct 19, 2020Updated 5 years ago
- VeeR EH1 core☆955Updated this week
- VeeR EL2 Core☆342Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,976Jul 14, 2026Updated last week
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆94Oct 14, 2020Updated 5 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- RISC-V CPU Core☆441Jun 24, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,266May 29, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,024Updated this week
- A simple superscalar out-of-order RISC-V microprocessor☆254Feb 24, 2025Updated last year
- RISC-V CPU Core (RV32IM)☆1,756Sep 18, 2021Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆193Nov 18, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,267Jun 27, 2024Updated 2 years ago
- RISC-V Cores, SoC platforms and SoCs☆928Mar 26, 2021Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,196Feb 11, 2026Updated 5 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 3 years ago
- GPGPU microprocessor architecture☆2,209Nov 8, 2024Updated last year
- ☆14Nov 5, 2017Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- ☆323Jan 23, 2026Updated 5 months ago
- VeeR EH2 core☆273Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆274Nov 6, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- Verilog Configurable Cache☆196Jun 10, 2026Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆341Dec 11, 2024Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆531Jun 8, 2026Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆622Jul 2, 2026Updated 2 weeks ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆130Aug 28, 2019Updated 6 years ago