Alternatives and similar repositories for riscv-sodor:

Users that are interested in riscv-sodor are comparing it to the libraries listed below

• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆570Updated 8 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆720Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆824Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,027Updated 7 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆632Updated 2 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,049Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆994Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆869Updated last year
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆649Updated 5 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆740Updated 8 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆695Updated last month
• riscv-software-src / riscv-tests
  ☆976Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,256Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆907Updated 5 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,097Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆870Updated 4 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,865Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆321Updated 10 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,514Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆601Updated this week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆407Updated 6 years ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆350Updated 7 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,817Updated this week
• riscv-non-isa / riscv-arch-test
  ☆554Updated 2 weeks ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆528Updated 3 weeks ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆596Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆521Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆419Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆678Updated last month