educational microarchitectures for risc-v isa
☆741Sep 1, 2025Updated 6 months ago
Alternatives and similar repositories for riscv-sodor
Users that are interested in riscv-sodor are comparing it to the libraries listed below
Sorting:
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- chisel tutorial exercises and answers☆748Jan 6, 2022Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,160Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,113Sep 10, 2024Updated last year
- Digital Design with Chisel☆899Feb 26, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,598Feb 28, 2026Updated last week
- A template project for beginning new Chisel work☆692Feb 24, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,153Feb 21, 2026Updated 2 weeks ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Feb 25, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- educational microarchitectures for risc-v isa☆67Feb 18, 2019Updated 7 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- A teaching-focused RISC-V CPU design used at UC Davis☆155Feb 5, 2023Updated 3 years ago
- Chisel examples and code snippets☆268Aug 1, 2022Updated 3 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- ☆1,133Jan 22, 2026Updated last month
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- Spike, a RISC-V ISA Simulator☆3,028Feb 26, 2026Updated last week
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- ☆87Jan 30, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆373Jul 12, 2017Updated 8 years ago
- ☆368Sep 12, 2025Updated 5 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆964Nov 15, 2024Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆162Jan 25, 2024Updated 2 years ago
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- ☆110Oct 19, 2018Updated 7 years ago
- Chisel components for FPGA projects☆128Sep 19, 2023Updated 2 years ago