Alternatives and similar repositories for riscv-sodor

Users that are interested in riscv-sodor are comparing it to the libraries listed below

• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆588Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆858Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,112Updated 3 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆747Updated last year
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,065Updated last year
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆609Updated 3 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆662Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,159Updated 3 months ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,963Updated 4 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆729Updated 2 weeks ago
• riscv-software-src / riscv-tests
  ☆1,053Updated 2 months ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆411Updated 6 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,091Updated 3 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆731Updated 3 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆588Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆494Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,626Updated last week
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆361Updated 8 years ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated 2 years ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆873Updated 5 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆553Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆440Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆511Updated 9 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,959Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆524Updated last week