VeeR EH1 core
☆931May 29, 2023Updated 2 years ago
Alternatives and similar repositories for Cores-VeeR-EH1
Users that are interested in Cores-VeeR-EH1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VeeR EL2 Core☆326Mar 12, 2026Updated 2 weeks ago
- ☆261Dec 22, 2022Updated 3 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆338Dec 11, 2024Updated last year
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 6 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,861Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,814Feb 17, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,203May 26, 2025Updated 10 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆973Nov 15, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,207Sep 18, 2021Updated 4 years ago
- Rocket Chip Generator☆3,730Feb 25, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,159Feb 21, 2026Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆787Updated this week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SERV - The SErial RISC-V CPU☆1,773Feb 19, 2026Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,116Mar 11, 2026Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆264Nov 6, 2024Updated last year
- RISC-V Cores, SoC platforms and SoCs☆920Mar 26, 2021Updated 5 years ago
- Random instruction generator for RISC-V processor verification☆1,270Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,090Feb 11, 2026Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 2 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆666Mar 8, 2026Updated 3 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,511Jan 7, 2026Updated 2 months ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- The OpenPiton Platform☆779Feb 25, 2026Updated last month
- The Ultra-Low Power RISC-V Core☆1,787Aug 6, 2025Updated 7 months ago
- OpenTitan: Open source silicon root of trust☆3,252Updated this week
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,194Updated this week
- Common SystemVerilog components☆728Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆580Mar 11, 2026Updated 2 weeks ago
- OmniXtend cache coherence protocol☆82Jun 10, 2025Updated 9 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- OpenXuantie - OpenC910 Core☆1,401Jun 28, 2024Updated last year
- RISC-V CPU Core (RV32IM)☆1,678Sep 18, 2021Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆228Aug 25, 2020Updated 5 years ago
- ☆153Oct 6, 2023Updated 2 years ago
- RISC-V CPU Core☆419Jun 24, 2025Updated 9 months ago
- RISC-V Formal Verification Framework☆626Apr 6, 2022Updated 3 years ago