Alternatives and similar repositories for Cores-VeeR-EH1:

Users that are interested in Cores-VeeR-EH1 are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,009Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,063Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆936Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,468Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆666Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆656Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,198Updated 2 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆639Updated 3 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆489Updated this week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆859Updated 4 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆896Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆570Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆591Updated 2 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆700Updated 6 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆859Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆559Updated 6 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆472Updated 2 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆610Updated 7 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆512Updated 4 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆801Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆588Updated 2 months ago
• riscv-non-isa / riscv-arch-test
  ☆537Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆454Updated this week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,207Updated 9 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆307Updated 8 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,479Updated 2 weeks ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,215Updated 7 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆471Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆225Updated 2 years ago