VeeR EH1 core
☆962Jul 16, 2026Updated last month
Alternatives and similar repositories for Cores-VeeR-EH1
Users that are interested in Cores-VeeR-EH1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VeeR EL2 Core☆344Updated this week
- VeeR EH2 core☆276Jul 20, 2026Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆342Dec 11, 2024Updated last year
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 6 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,073Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,023Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,277May 29, 2026Updated 2 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆997Nov 15, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,290Sep 18, 2021Updated 4 years ago
- Rocket Chip Generator☆3,850Jun 2, 2026Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,663Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,195Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,351Jul 31, 2026Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆827Jul 13, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,224Aug 11, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,869Jul 10, 2026Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆277Nov 6, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,347Apr 3, 2026Updated 4 months ago
- RISC-V Cores, SoC platforms and SoCs☆927Mar 26, 2021Updated 5 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆711Aug 13, 2026Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 7 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,233Feb 11, 2026Updated 6 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,599May 12, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- The OpenPiton Platform☆810Feb 25, 2026Updated 5 months ago
- OpenXuantie - OpenC910 Core☆1,467Jun 28, 2024Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,900Aug 6, 2025Updated last year
- OpenTitan: Open source silicon root of trust☆3,604Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆632Jul 24, 2026Updated last month
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆382Jul 12, 2017Updated 9 years ago
- Common SystemVerilog components☆788Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,365Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- OmniXtend cache coherence protocol☆85Jun 10, 2025Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆302Jul 27, 2026Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- RISC-V CPU Core (RV32IM)☆1,770Sep 18, 2021Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 5 years ago
- RISC-V CPU Core☆444Jun 24, 2025Updated last year
- ☆157Oct 6, 2023Updated 2 years ago