Alternatives and similar repositories for Cores-VeeR-EH1

Users that are interested in Cores-VeeR-EH1 are comparing it to the libraries listed below

• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,144Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,595Updated last week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆871Updated 5 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,069Updated 3 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆723Updated 2 weeks ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆925Updated 8 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆895Updated 4 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,339Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆572Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆719Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆642Updated last week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆549Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆605Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆516Updated 5 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 4 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,438Updated 5 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,296Updated last year
• riscv-non-isa / riscv-arch-test
  ☆580Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,318Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆653Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,617Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆852Updated last month
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆585Updated 11 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,091Updated 4 months ago