A small, light weight, RISC CPU soft core
☆1,570Dec 8, 2025Updated 8 months ago
Alternatives and similar repositories for zipcpu
Users that are interested in zipcpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,597May 12, 2026Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,218Feb 11, 2026Updated 5 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,309Jul 31, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,852Jul 10, 2026Updated 3 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,060Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog library for ASIC and FPGA designers☆1,435May 8, 2024Updated 2 years ago
- A simple, basic, formally verified UART controller☆346Jan 29, 2024Updated 2 years ago
- Bus bridges and other odds and ends☆691Jun 2, 2026Updated 2 months ago
- GPGPU microprocessor architecture☆2,213Nov 8, 2024Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆587Jun 6, 2026Updated 2 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,004Jul 28, 2026Updated last week
- Must-have verilog systemverilog modules☆2,006Mar 12, 2026Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆1,286Sep 18, 2021Updated 4 years ago
- RISC-V CPU Core (RV32IM)☆1,763Sep 18, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆46Oct 27, 2022Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,893Aug 6, 2025Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,650Updated this week
- Common SystemVerilog components☆777Jul 29, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆992Nov 15, 2024Updated last year
- A utility for Composing FPGA designs from Peripherals☆192Jul 4, 2026Updated last month
- Various HDL (Verilog) IP Cores☆929Jul 1, 2021Updated 5 years ago
- Verilog AXI components for FPGA implementation☆2,109Feb 27, 2025Updated last year
- Build your hardware, easily!☆4,034Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Yosys Open SYnthesis Suite☆4,656Updated this week
- Verilog Ethernet components for FPGA implementation☆3,058Feb 27, 2025Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆677Jul 7, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,446Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,826Updated this week
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,221Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Rocket Chip Generator☆3,840Jun 2, 2026Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆824Jul 13, 2026Updated 3 weeks ago
- Chisel: A Modern Hardware Design Language☆4,754Updated this week
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,850Mar 24, 2021Updated 5 years ago
- Hardware Description Languages☆1,165Jul 9, 2026Updated last month
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆384Oct 19, 2023Updated 2 years ago