RISC-V CPU Core
☆411Jun 24, 2025Updated 8 months ago
Alternatives and similar repositories for RV12
Users that are interested in RV12 are comparing it to the libraries listed below
Sorting:
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- An open-source microcontroller system based on RISC-V☆1,010Feb 6, 2024Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated 2 weeks ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Feb 28, 2018Updated 8 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆259Nov 6, 2024Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆137Oct 2, 2025Updated 5 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,493Jan 7, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆226Aug 25, 2020Updated 5 years ago
- ☆258Dec 22, 2022Updated 3 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆192Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,152Feb 21, 2026Updated last week
- Rocket Chip Generator☆3,696Updated this week
- Common SystemVerilog components☆713Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆661Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆297Feb 4, 2026Updated last month
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated last week
- VeeR EL2 Core☆318Feb 23, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆320Feb 24, 2026Updated last week
- RISC-V Formal Verification Framework☆625Apr 6, 2022Updated 3 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 5 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆570Oct 21, 2025Updated 4 months ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆684Jul 16, 2025Updated 7 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated 3 weeks ago
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 3 weeks ago