Alternatives and similar repositories for RV12

Users that are interested in RV12 are comparing it to the libraries listed below

• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆335Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆251Updated 3 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆309Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆689Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆250Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆279Updated 5 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆451Updated 7 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆222Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆631Updated last week
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆188Updated last week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆312Updated 10 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆628Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆204Updated last year
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆329Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆236Updated last year
• riscv-non-isa / riscv-arch-test
  ☆622Updated this week
• ucb-bar / berkeley-hardfloat
  ☆362Updated 3 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆309Updated last week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆678Updated 5 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆568Updated 4 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆620Updated 3 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆533Updated last year