RoaLogic / RV12
RISC-V CPU Core
☆324Updated 10 months ago
Alternatives and similar repositories for RV12:
Users that are interested in RV12 are comparing it to the libraries listed below
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- ☆232Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆485Updated 2 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆250Updated 2 weeks ago
- Common SystemVerilog components☆608Updated 2 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆315Updated 4 months ago
- VeeR EL2 Core☆274Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆528Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆231Updated 6 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆420Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆226Updated 5 months ago
- A simple RISC-V processor for use in FPGA designs.☆271Updated 8 months ago
- RISC-V Torture Test☆192Updated 9 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆570Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆649Updated 5 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆210Updated 3 weeks ago
- Bus bridges and other odds and ends☆551Updated 3 weeks ago
- CORE-V Family of RISC-V Cores☆264Updated 2 months ago
- RISC-V microcontroller IP core developed in Verilog☆175Updated 3 weeks ago
- ☆283Updated last month
- Verilog Configurable Cache☆178Updated 5 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆419Updated 2 weeks ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆366Updated last year
- Basic RISC-V Test SoC☆122Updated 6 years ago
- RISC-V Formal Verification Framework☆599Updated 3 years ago
- ☆321Updated 7 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆323Updated 3 years ago
- ☆556Updated this week