RISC-V CPU Core
☆417Jun 24, 2025Updated 8 months ago
Alternatives and similar repositories for RV12
Users that are interested in RV12 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- An open-source microcontroller system based on RISC-V☆1,017Feb 6, 2024Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Feb 28, 2018Updated 8 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,804Feb 17, 2026Updated last month
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,501Jan 7, 2026Updated 2 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆140Oct 2, 2025Updated 5 months ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆303Feb 4, 2026Updated last month
- Common SystemVerilog components☆728Updated this week
- ☆261Dec 22, 2022Updated 3 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆264Nov 6, 2024Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆228Aug 25, 2020Updated 5 years ago
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- ☆10Nov 8, 2019Updated 6 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 5 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆193Updated this week
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- Platform Level Interrupt Controller☆46May 10, 2024Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆323Updated this week
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- VeeR EL2 Core☆323Mar 12, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- RISC-V Formal Verification Framework☆625Apr 6, 2022Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆663Mar 8, 2026Updated 2 weeks ago
- A simple RISC-V processor for use in FPGA designs.☆285Aug 19, 2024Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆338Dec 11, 2024Updated last year
- CORE-V Family of RISC-V Cores☆340Feb 13, 2025Updated last year