RoaLogic / RV12Links
RISC-V CPU Core
☆393Updated 4 months ago
Alternatives and similar repositories for RV12
Users that are interested in RV12 are comparing it to the libraries listed below
Sorting:
- RISC-V Debug Support for our PULP RISC-V Cores☆280Updated last week
- VeeR EL2 Core☆303Updated this week
- Instruction Set Generator initially contributed by Futurewei☆300Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- ☆247Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆542Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- Common SystemVerilog components☆673Updated 3 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆446Updated 6 months ago
- RISC-V Torture Test☆202Updated last year
- ☆300Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆614Updated last month
- CORE-V Family of RISC-V Cores☆304Updated 9 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated this week
- A simple RISC-V processor for use in FPGA designs.☆282Updated last year
- ☆607Updated this week
- ☆355Updated 2 months ago
- RISC-V soft-core microcontroller for FPGA implementation☆186Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆616Updated this week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆520Updated 11 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago
- RISC-V Formal Verification Framework☆616Updated 3 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆299Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆496Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆274Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆468Updated 3 months ago
- A Linux-capable RISC-V multicore for and by the world☆747Updated last week