Alternatives and similar repositories for hw

Users that are interested in hw are comparing it to the libraries listed below

• nvdla / doc
  Documentation for NVDLA.
  ☆260Updated 6 months ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,195Updated this week
• nvdla / sw
  NVDLA SW
  ☆511Updated 4 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,392Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,162Updated 8 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,469Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,384Updated last year
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,933Updated 10 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,243Updated 3 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆857Updated 10 months ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,518Updated last year
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆713Updated 2 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,707Updated 5 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆908Updated 4 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,101Updated last year
• dgschwend / zynqnet
  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
  ☆767Updated 8 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆919Updated 2 years ago
• fengbintu / Neural-Networks-on-Silicon
  This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…
  ☆2,048Updated 2 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,115Updated last week
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆437Updated 6 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,746Updated this week
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆534Updated 7 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆415Updated 6 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆860Updated last year
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,224Updated last week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆744Updated 4 years ago
• vortexgpgpu / vortex
  ☆1,874Updated this week
• doonny / PipeCNN
  An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
  ☆1,366Updated 3 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,173Updated 4 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,046Updated last week