Alternatives and similar repositories for hw

Users that are interested in hw are comparing it to the libraries listed below

• nvdla / doc
  Documentation for NVDLA.
  ☆255Updated 2 months ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,066Updated last month
• dgschwend / zynqnet
  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
  ☆760Updated 8 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,339Updated last year
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,326Updated last year
• nvdla / sw
  NVDLA SW
  ☆506Updated 4 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,068Updated last year
• doonny / PipeCNN
  An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
  ☆1,345Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,382Updated 2 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,986Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,175Updated last week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,823Updated 7 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,123Updated 4 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,617Updated 2 months ago
• fengbintu / Neural-Networks-on-Silicon
  This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…
  ☆2,012Updated 2 months ago
• Xilinx / BNN-PYNQ
  Quantized Neural Networks (QNNs) on PYNQ
  ☆702Updated 3 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,435Updated last year
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆831Updated 7 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,635Updated 2 weeks ago
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,124Updated 11 months ago
• vortexgpgpu / vortex
  ☆1,683Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,628Updated last week
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆430Updated 5 years ago
• hunterlew / convolution_network_on_FPGA
  CNN acceleration on virtex-7 FPGA with verilog HDL
  ☆462Updated 7 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆735Updated 3 years ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆509Updated 6 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆674Updated 2 years ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,843Updated 2 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,102Updated last week
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆976Updated last year