Alternatives and similar repositories for hw

Users that are interested in hw are comparing it to the libraries listed below

• nvdla / doc
  Documentation for NVDLA.
  ☆251Updated last month
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,023Updated 4 months ago
• nvdla / sw
  NVDLA SW
  ☆503Updated 4 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,937Updated last week
• fengbintu / Neural-Networks-on-Silicon
  This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…
  ☆1,998Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,795Updated 5 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• doonny / PipeCNN
  An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
  ☆1,329Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,356Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,061Updated 11 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,301Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,110Updated 3 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,571Updated 3 weeks ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆739Updated 3 years ago
• dgschwend / zynqnet
  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
  ☆757Updated 8 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆895Updated 4 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,410Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,615Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,132Updated this week
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆410Updated 6 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆822Updated 5 months ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆850Updated 7 months ago
• vortexgpgpu / vortex
  ☆1,629Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,597Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆666Updated 2 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,960Updated 3 months ago
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,107Updated 9 months ago
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆497Updated 6 years ago