Alternatives and similar repositories for hw:

Users that are interested in hw are comparing it to the libraries listed below

• nvdla / doc
  Documentation for NVDLA.
  ☆246Updated 7 months ago
• nvdla / sw
  NVDLA SW
  ☆493Updated 4 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,263Updated 10 months ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆900Updated last month
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,018Updated 6 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,655Updated last month
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,252Updated 11 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,242Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,029Updated last month
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,792Updated this week
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,237Updated 9 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,081Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,068Updated this week
• KastnerRG / riffa
  The RIFFA development repository
  ☆808Updated 9 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,441Updated 5 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,500Updated last month
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆408Updated 6 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆714Updated 3 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,848Updated last week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,924Updated this week
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆814Updated 2 months ago
• vortexgpgpu / vortex
  ☆1,455Updated last week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆792Updated last month
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆943Updated last year
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆867Updated 4 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆972Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆864Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,414Updated this week
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆712Updated 2 weeks ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆690Updated 9 months ago