nvdla / hwLinks
RTL, Cmodel, and testbench for NVDLA
☆1,964Updated 3 years ago
Alternatives and similar repositories for hw
Users that are interested in hw are comparing it to the libraries listed below
Sorting:
- Documentation for NVDLA.☆258Updated 3 months ago
- NVDLA SW☆508Updated 4 years ago
- Berkeley's Spatial Array Generator☆1,109Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,036Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,405Updated last week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,082Updated last year
- OpenXuantie - OpenC910 Core☆1,342Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,138Updated 5 months ago
- Random instruction generator for RISC-V processor verification☆1,196Updated last month
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,356Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,359Updated last year
- Verilog AXI components for FPGA implementation☆1,854Updated 8 months ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆763Updated 8 years ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,031Updated last week
- chisel tutorial exercises and answers☆734Updated 3 years ago
- Verilog PCI express components☆1,456Updated last year
- The Ultra-Low Power RISC-V Core☆1,644Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,676Updated 2 months ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆864Updated last month
- VeeR EH1 core☆906Updated 2 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆702Updated 3 years ago
- ☆1,753Updated this week
- RISC-V Cores, SoC platforms and SoCs☆902Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆412Updated 6 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆435Updated 5 years ago
- Vitis_Accel_Examples☆569Updated 3 months ago
- synthesiseable ieee 754 floating point library in verilog☆693Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,681Updated last week
- Verilog AXI stream components for FPGA implementation☆840Updated 8 months ago
- ☆740Updated 4 months ago