Alternatives and similar repositories for hw

Users that are interested in hw are comparing it to the libraries listed below

• nvdla / doc
  Documentation for NVDLA.
  ☆248Updated 10 months ago
• nvdla / sw
  NVDLA SW
  ☆497Updated 4 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,037Updated 8 months ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆957Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,293Updated last year
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,860Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆728Updated 3 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,508Updated 7 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,128Updated 3 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,274Updated 11 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,287Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆879Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,553Updated this week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,724Updated 3 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated last week
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆421Updated 5 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,904Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆706Updated 2 weeks ago
• vortexgpgpu / vortex
  ☆1,522Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆837Updated 3 weeks ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,312Updated last year
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,170Updated 2 years ago
• Xilinx / BNN-PYNQ
  Quantized Neural Networks (QNNs) on PYNQ
  ☆689Updated 3 years ago
• Xilinx / XRT
  Run Time for AIE and FPGA based platforms
  ☆595Updated last week
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,083Updated 6 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,103Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆808Updated 3 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,410Updated 3 months ago
• dgschwend / zynqnet
  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
  ☆753Updated 8 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆408Updated 6 years ago