nvdla / hwLinks
RTL, Cmodel, and testbench for NVDLA
☆2,007Updated 3 years ago
Alternatives and similar repositories for hw
Users that are interested in hw are comparing it to the libraries listed below
Sorting:
- Documentation for NVDLA.☆260Updated 5 months ago
- Berkeley's Spatial Array Generator☆1,169Updated this week
- NVDLA SW☆511Updated 4 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,097Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,447Updated 3 weeks ago
- OpenXuantie - OpenC910 Core☆1,366Updated last year
- Verilog AXI components for FPGA implementation☆1,906Updated 10 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,156Updated 7 months ago
- Verilog library for ASIC and FPGA designers☆1,379Updated last year
- Random instruction generator for RISC-V processor verification☆1,232Updated 3 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,082Updated last week
- Verilog PCI express components☆1,496Updated last year
- The Ultra-Low Power RISC-V Core☆1,690Updated 4 months ago
- chisel tutorial exercises and answers☆739Updated 3 years ago
- Verilog AXI stream components for FPGA implementation☆852Updated 10 months ago
- Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"☆767Updated 8 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,739Updated this week
- GPGPU microprocessor architecture☆2,164Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,719Updated last week
- RISC-V Cores, SoC platforms and SoCs☆907Updated 4 years ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,361Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆706Updated 2 years ago
- ☆1,838Updated last week
- VeeR EH1 core☆917Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,042Updated this week
- Support for Rocket Chip on Zynq FPGAs☆414Updated 6 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,035Updated last month
- Rocket Chip Generator☆3,654Updated last week
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,046Updated last month
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,797Updated 4 years ago