westerndigitalcorporation / omnixtendLinks
An open standard Cache Coherent Fabric Interface repository
☆66Updated 5 years ago
Alternatives and similar repositories for omnixtend
Users that are interested in omnixtend are comparing it to the libraries listed below
Sorting:
- OmniXtend cache coherence protocol☆82Updated 4 months ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 4 years ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆106Updated 7 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Connectal is a framework for software-driven hardware development.☆174Updated last year
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- ☆141Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆54Updated 3 years ago
- A time-predictable processor for mixed-criticality systems☆58Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- ☆248Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆159Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Network Development Kit (NDK) for FPGA cards with example application☆66Updated last week
- ☆89Updated last month
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- CAPI SNAP Framework Hardware and Software☆110Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 8 months ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- ☆63Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 9 months ago
- Open Programmable Acceleration Engine☆266Updated 2 months ago
- The OpenRISC 1000 architectural simulator☆75Updated 5 months ago