Alternatives and similar repositories for omnixtend

Users that are interested in omnixtend are comparing it to the libraries listed below

• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated last month
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆203Updated 4 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆104Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆171Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆110Updated 2 years ago
• openpower-cores / a2i
  ☆247Updated 2 years ago
• openpower-cores / a2o
  ☆140Updated 3 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆59Updated 9 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆159Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 3 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆64Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆182Updated 7 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆63Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆39Updated 2 years ago
• CESNET / ndk-fpga
  Network Development Kit (NDK) for FPGA cards with example application
  ☆59Updated this week
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆53Updated 3 years ago
• ReconOS / reconos
  ReconOS - Operating System for Reconfigurable Hardware
  ☆29Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated last week
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆56Updated 5 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆27Updated 5 years ago