Alternatives and similar repositories for serv

Users that are interested in serv are comparing it to the libraries listed below

• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,974Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,999Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,751Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆684Updated last month
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,385Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,504Updated 2 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,341Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,604Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆922Updated 2 years ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,540Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,044Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,928Updated last year
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,127Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆759Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆743Updated last week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,918Updated this week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,715Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆960Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,248Updated 4 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆699Updated 2 months ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,485Updated last month
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆696Updated last week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,791Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,248Updated last week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,133Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆847Updated 8 months ago