olofk / serv

Related projects ⓘ

Alternatives and complementary repositories for serv

• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,501Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆863Updated 3 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆585Updated 4 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,299Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆818Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,199Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,592Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,305Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆959Updated 3 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated last week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,132Updated 4 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆620Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆860Updated last month
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆841Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,213Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆831Updated 4 months ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆965Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆642Updated 3 weeks ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆598Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆557Updated 2 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,183Updated 6 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆587Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆584Updated 2 years ago
• cocotb / cocotb
  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  ☆1,802Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,017Updated 2 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,255Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,095Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆774Updated last week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,115Updated 3 weeks ago