lowRISC / opentitanLinks
OpenTitan: Open source silicon root of trust
☆2,903Updated this week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,595Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,568Updated this week
- Random instruction generator for RISC-V processor verification☆1,144Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,944Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,098Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,834Updated 3 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,915Updated this week
- VeeR EH1 core☆885Updated 2 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,014Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,374Updated 2 weeks ago
- RISC-V Cores, SoC platforms and SoCs☆894Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,050Updated this week
- Rocket Chip Generator☆3,502Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,603Updated last year
- A small, light weight, RISC CPU soft core☆1,438Updated 5 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆948Updated last month
- OpenXuantie - OpenC910 Core☆1,291Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,595Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,313Updated last month
- SERV - The SErial RISC-V CPU☆1,615Updated last month
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,823Updated this week
- A directory of Western Digital’s RISC-V SweRV Cores☆871Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,066Updated 3 years ago
- Scala based HDL☆1,829Updated last week
- RISC-V Tools (ISA Simulator and Tests)☆1,171Updated 2 years ago
- The OpenPiton Platform☆721Updated last week
- An Open-source FPGA IP Generator☆964Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,339Updated last week
- An open-source microcontroller system based on RISC-V☆968Updated last year
- Build your hardware, easily!☆3,426Updated this week