OpenTitan: Open source silicon root of trust
☆3,376May 19, 2026Updated this week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated last week
- Random instruction generator for RISC-V processor verification☆1,298Apr 3, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,581Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- VeeR EH1 core☆942May 29, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- Common SystemVerilog components☆747May 7, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,085Mar 2, 2022Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,371Updated this week
- Rocket Chip Generator☆3,768Apr 21, 2026Updated 3 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,846Mar 13, 2026Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- Verilator open-source SystemVerilog simulator and lint system☆3,604May 12, 2026Updated last week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- Yosys Open SYnthesis Suite☆4,443Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,142Feb 11, 2026Updated 3 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,251Apr 29, 2026Updated 2 weeks ago
- The OpenPiton Platform☆790Feb 25, 2026Updated 2 months ago
- IC design and development should be faster,simpler and more reliable☆1,993Dec 31, 2021Updated 4 years ago
- AMBA AXI VIP☆457Jun 28, 2024Updated last year
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Chisel: A Modern Hardware Design Language☆4,661Updated this week
- Open-source high-performance RISC-V processor☆7,023Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆664May 11, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆375May 13, 2026Updated last week
- Verilog PCI express components☆1,596Apr 26, 2024Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆980Nov 15, 2024Updated last year
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated 3 weeks ago
- Must-have verilog systemverilog modules☆1,958Mar 12, 2026Updated 2 months ago
- ☆2,013Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A Linux-capable RISC-V multicore for and by the world☆801Apr 24, 2026Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,795Feb 19, 2026Updated 3 months ago
- Verilog AXI components for FPGA implementation☆2,044Feb 27, 2025Updated last year
- Awesome ASIC design verification☆355Feb 9, 2022Updated 4 years ago
- RISC-V Formal Verification Framework☆631Apr 6, 2022Updated 4 years ago
- SystemVerilog to Verilog conversion☆728Mar 28, 2026Updated last month
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,787Mar 25, 2026Updated last month