OpenTitan: Open source silicon root of trust
☆3,266Mar 31, 2026Updated last week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,824Feb 17, 2026Updated last month
- Random instruction generator for RISC-V processor verification☆1,276Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,539Mar 31, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,873Mar 23, 2026Updated 2 weeks ago
- VeeR EH1 core☆933May 29, 2023Updated 2 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Functional verification project for the CORE-V family of RISC-V cores.☆671Mar 8, 2026Updated 3 weeks ago
- Common SystemVerilog components☆727Mar 31, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,401Feb 13, 2026Updated last month
- RTL, Cmodel, and testbench for NVDLA☆2,045Mar 2, 2022Updated 4 years ago
- Rocket Chip Generator☆3,732Feb 25, 2026Updated last month
- cocotb: Python-based chip (RTL) verification☆2,312Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,804Mar 13, 2026Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,205May 26, 2025Updated 10 months ago
- Verilator open-source SystemVerilog simulator and lint system☆3,490Mar 31, 2026Updated last week
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Code generation tool for control and status registers☆450Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,077Jun 27, 2024Updated last year
- Yosys Open SYnthesis Suite☆4,385Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,095Feb 11, 2026Updated last month
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,202Updated this week
- The OpenPiton Platform☆779Feb 25, 2026Updated last month
- AMBA AXI VIP☆452Jun 28, 2024Updated last year
- IC design and development should be faster,simpler and more reliable☆1,986Dec 31, 2021Updated 4 years ago
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Chisel: A Modern Hardware Design Language☆4,626Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆370Mar 31, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆657Updated this week
- Open-source high-performance RISC-V processor☆6,958Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆974Nov 15, 2024Updated last year
- An abstraction library for interfacing EDA tools☆757Apr 1, 2026Updated last week
- Must-have verilog systemverilog modules☆1,945Mar 12, 2026Updated 3 weeks ago
- Verilog PCI express components☆1,564Apr 26, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆789Apr 1, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- SERV - The SErial RISC-V CPU☆1,776Feb 19, 2026Updated last month
- ☆1,957Updated this week
- SystemVerilog to Verilog conversion☆711Mar 28, 2026Updated last week
- Verilog AXI components for FPGA implementation☆2,001Feb 27, 2025Updated last year
- Awesome ASIC design verification☆348Feb 9, 2022Updated 4 years ago
- RISC-V Formal Verification Framework☆628Apr 6, 2022Updated 4 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,734Mar 25, 2026Updated last week