Alternatives and similar repositories for opentitan

Users that are interested in opentitan are comparing it to the libraries listed below

• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,567Updated last week
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,503Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,921Updated last month
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,797Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,133Updated 2 weeks ago
• firesim / firesim
  FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
  ☆935Updated last week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,344Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆882Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,079Updated 3 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,028Updated this week
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆885Updated 4 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,600Updated 2 weeks ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,872Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,418Updated 4 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,866Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆710Updated 3 weeks ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,471Updated 3 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,530Updated 11 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆745Updated 9 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,036Updated 3 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆708Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,300Updated last year
• chipsalliance / chisel
  Chisel: A Modern Hardware Design Language
  ☆4,298Updated this week
• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,509Updated 3 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆869Updated 5 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,034Updated last year
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,946Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,168Updated 2 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated 2 weeks ago