OpenTitan: Open source silicon root of trust
☆3,553Jul 19, 2026Updated this week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,976Updated this week
- Random instruction generator for RISC-V processor verification☆1,325Apr 3, 2026Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,625Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,024Updated this week
- VeeR EH1 core☆955Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Functional verification project for the CORE-V family of RISC-V cores.☆700Updated this week
- Common SystemVerilog components☆766Updated this week
- Rocket Chip Generator☆3,820Jun 2, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,435Jul 2, 2026Updated 2 weeks ago
- RTL, Cmodel, and testbench for NVDLA☆2,121Mar 2, 2022Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,447Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,892Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,266May 29, 2026Updated last month
- Verilator open-source SystemVerilog simulator and lint system☆3,754Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Code generation tool for control and status registers☆462Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,335Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,267Jun 27, 2024Updated 2 years ago
- Yosys Open SYnthesis Suite☆4,612Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,196Feb 11, 2026Updated 5 months ago
- The OpenPiton Platform☆802Feb 25, 2026Updated 4 months ago
- AMBA AXI VIP☆468Jun 28, 2024Updated 2 years ago
- IC design and development should be faster，simpler and more reliable☆2,001Dec 31, 2021Updated 4 years ago
- Chisel: A Modern Hardware Design Language☆4,729Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open-source high-performance RISC-V processor☆7,149Updated this week
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆379Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆674Jul 7, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆989Nov 15, 2024Updated last year
- Verilog PCI express components☆1,626Apr 26, 2024Updated 2 years ago
- Awesome ASIC design verification☆363Feb 9, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆780Jul 2, 2026Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆823Jul 13, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆2,162Updated this week
- SERV - The SErial RISC-V CPU☆1,831Jul 10, 2026Updated last week
- Verilog AXI components for FPGA implementation☆2,095Feb 27, 2025Updated last year
- Must-have verilog systemverilog modules☆1,997Mar 12, 2026Updated 4 months ago
- SystemVerilog to Verilog conversion☆741Mar 28, 2026Updated 3 months ago
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- Build your hardware, easily!☆3,998Updated this week