OpenTitan: Open source silicon root of trust
☆3,152Updated this week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,771Feb 17, 2026Updated last week
- Random instruction generator for RISC-V processor verification☆1,253Oct 1, 2025Updated 4 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,817Feb 18, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- VeeR EH1 core☆927May 29, 2023Updated 2 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆661Updated this week
- Common SystemVerilog components☆712Feb 6, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,685Feb 17, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,187May 26, 2025Updated 9 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,389Feb 13, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,776Dec 22, 2025Updated 2 months ago
- Yosys Open SYnthesis Suite☆4,293Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,143Updated this week
- cocotb: Python-based chip (RTL) verification☆2,255Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,026Feb 11, 2026Updated 2 weeks ago
- RTL, Cmodel, and testbench for NVDLA☆2,025Mar 2, 2022Updated 3 years ago
- Verilator open-source SystemVerilog simulator and lint system☆3,363Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,966Jun 27, 2024Updated last year
- Code generation tool for control and status registers☆445Jan 7, 2026Updated last month
- The OpenPiton Platform☆770Sep 24, 2025Updated 5 months ago
- Chisel: A Modern Hardware Design Language☆4,588Updated this week
- SERV - The SErial RISC-V CPU☆1,751Feb 19, 2026Updated last week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,714Sep 15, 2025Updated 5 months ago
- AMBA AXI VIP☆449Jun 28, 2024Updated last year
- Build your hardware, easily!☆3,739Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- IC design and development should be faster，simpler and more reliable☆1,985Dec 31, 2021Updated 4 years ago
- An open-source static random access memory (SRAM) compiler.☆1,012Jan 16, 2026Updated last month
- A Linux-capable RISC-V multicore for and by the world☆764Feb 9, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- Verilog PCI express components☆1,539Apr 26, 2024Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,079Feb 5, 2026Updated 3 weeks ago
- Open-source high-performance RISC-V processor☆6,875Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆359Feb 19, 2026Updated last week
- An abstraction library for interfacing EDA tools☆755Feb 18, 2026Updated last week
- RISC-V Formal Verification Framework☆625Apr 6, 2022Updated 3 years ago
- An Open-source FPGA IP Generator☆1,051Updated this week
- SystemVerilog to Verilog conversion☆704Nov 24, 2025Updated 3 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,432Feb 19, 2026Updated last week