OpenTitan: Open source silicon root of trust
☆3,683Oct 8, 2026Updated this week
Alternatives and similar repositories for opentitan
Users that are interested in opentitan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,087Updated this week
- Random instruction generator for RISC-V processor verification☆1,362Sep 21, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,714Sep 24, 2026Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,150Updated this week
- VeeR EH1 core☆971Jul 16, 2026Updated 2 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Functional verification project for the CORE-V family of RISC-V cores.☆728Sep 14, 2026Updated 3 weeks ago
- Common SystemVerilog components☆807Sep 18, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,881Sep 13, 2026Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,472Sep 25, 2026Updated 2 weeks ago
- RTL, Cmodel, and testbench for NVDLA☆2,176Mar 2, 2022Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,538Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,953Sep 23, 2026Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,309Oct 1, 2026Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,990Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,391Sep 7, 2026Updated last month
- Code generation tool for control and status registers☆471Sep 11, 2026Updated 3 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,414Updated this week
- Yosys Open SYnthesis Suite☆4,790Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,281Sep 27, 2026Updated last week
- The OpenPiton Platform☆832Feb 25, 2026Updated 7 months ago
- AMBA AXI VIP☆478Oct 1, 2026Updated last week
- IC design and development should be faster，simpler and more reliable☆2,026Dec 31, 2021Updated 4 years ago
- Chisel: A Modern Hardware Design Language☆4,807Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- OpenXuantie - OpenC910 Core☆1,479Jun 28, 2024Updated 2 years ago
- Open-source high-performance RISC-V processor☆7,295Updated this week
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- ☆2,296Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆398Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆689Sep 28, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,006Nov 15, 2024Updated last year
- Verilog PCI express components☆1,666Apr 26, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Awesome ASIC design verification☆368Feb 9, 2022Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆835Updated this week
- SERV - The SErial RISC-V CPU☆1,900Aug 25, 2026Updated last month
- Verilog AXI components for FPGA implementation☆2,149Feb 27, 2025Updated last year
- Must-have verilog systemverilog modules☆2,024Mar 12, 2026Updated 6 months ago
- SystemVerilog to Verilog conversion☆754Aug 18, 2026Updated last month
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago