Alternatives and similar repositories for raven-picorv32:

Users that are interested in raven-picorv32 are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆570Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆307Updated 8 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆402Updated 3 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆454Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆518Updated last week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆297Updated 9 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆225Updated 2 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated 2 weeks ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆111Updated 5 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆263Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆259Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆489Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆241Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆248Updated last week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆287Updated last year
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆225Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆232Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆547Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆443Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆267Updated 5 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆271Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆125Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆377Updated 7 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆138Updated 7 months ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆146Updated 7 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆182Updated last year
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆472Updated 2 months ago