Alternatives and similar repositories for raven-picorv32

Users that are interested in raven-picorv32 are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆327Updated 11 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆278Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 5 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆125Updated 6 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆257Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆560Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆214Updated 4 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated 2 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆349Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆467Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆497Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆333Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆545Updated 2 weeks ago
• jamieiles / uart
  Verilog UART
  ☆165Updated 11 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆251Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated this week
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆205Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆261Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆401Updated 11 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆177Updated last month
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆414Updated last week
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆147Updated 11 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆274Updated 9 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆157Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 7 months ago