Silicon-validated SoC implementation of the PicoSoc/PicoRV32
☆299Jul 28, 2020Updated 6 years ago
Alternatives and similar repositories for raven-picorv32
Users that are interested in raven-picorv32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,392Sep 7, 2026Updated last month
- Completed LDO Design for Skywaters 130nm☆21Feb 16, 2023Updated 3 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆415Feb 26, 2025Updated last year
- ☆18Nov 4, 2024Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆51Feb 7, 2025Updated last year
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,122Updated this week
- Testbenches for HDL projects☆23Oct 13, 2026Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆138Feb 22, 2022Updated 4 years ago
- RISC-V CPU Core☆453Jun 24, 2025Updated last year
- 32-bit RISC-V microcontroller☆13Sep 11, 2021Updated 5 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆30Oct 3, 2023Updated 3 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,007Nov 15, 2024Updated last year
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An open-source static random access memory (SRAM) compiler.☆1,160Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- SERV - The SErial RISC-V CPU☆1,903Aug 25, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,164Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆501May 8, 2026Updated 5 months ago
- 32-bit Superscalar RISC-V CPU☆1,319Sep 18, 2021Updated 5 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆236Oct 26, 2024Updated last year
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,977Mar 25, 2026Updated 6 months ago
- Magic VLSI Layout Tool☆722Oct 8, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Using VexRiscv without installing Scala☆40Nov 10, 2021Updated 4 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,855Mar 24, 2021Updated 5 years ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,298Oct 12, 2026Updated last week
- VeeR EH1 core☆971Jul 16, 2026Updated 3 months ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆149Sep 26, 2026Updated 3 weeks ago
- Common SystemVerilog components☆808Sep 18, 2026Updated last month
- Formulated testbench using System Verilog and UVM and verified I2C bus controller with APB interface☆14Dec 8, 2020Updated 5 years ago
- USB 1.1 Device IP Core☆21Oct 1, 2017Updated 9 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 6 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆257Sep 24, 2026Updated 3 weeks ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Aug 28, 2019Updated 7 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆248Jul 16, 2023Updated 3 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- ☆66Dec 16, 2018Updated 7 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 7 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,628Oct 12, 2026Updated last week