VerticalResearchGroup / miaowLinks
An open source GPU based off of the AMD Southern Islands ISA.
☆1,174Updated 7 years ago
Alternatives and similar repositories for miaow
Users that are interested in miaow are comparing it to the libraries listed below
Sorting:
- GPGPU microprocessor architecture☆2,083Updated 6 months ago
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,003Updated 6 months ago
- GPL v3 2D/3D graphics engine in verilog☆665Updated 10 years ago
- ☆1,522Updated last week
- An open-source microcontroller system based on RISC-V☆957Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,900Updated 3 weeks ago
- A small, light weight, RISC CPU soft core☆1,409Updated 3 months ago
- VeeR EH1 core☆879Updated 2 years ago
- Verilog library for ASIC and FPGA designers☆1,293Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,553Updated this week
- 32-bit Superscalar RISC-V CPU☆1,024Updated 3 years ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,492Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,782Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,328Updated last week
- mor1kx - an OpenRISC 1000 processor IP core☆538Updated 2 months ago
- The OpenPiton Platform☆706Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,077Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 6 months ago
- A Linux-capable RISC-V multicore for and by the world☆701Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,293Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,506Updated 11 months ago
- Scala based HDL☆1,794Updated this week
- educational microarchitectures for risc-v isa☆714Updated 2 months ago
- An open-source static random access memory (SRAM) compiler.☆906Updated 2 months ago
- Flexible Intermediate Representation for RTL☆741Updated 9 months ago
- The root repo for lowRISC project and FPGA demos.☆600Updated last year
- synthesiseable ieee 754 floating point library in verilog☆638Updated 2 years ago
- SERV - The SErial RISC-V CPU☆1,589Updated 2 weeks ago
- chisel tutorial exercises and answers☆728Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,126Updated 3 months ago