Alternatives and similar repositories for miaow

Users that are interested in miaow are comparing it to the libraries listed below

• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,115Updated 10 months ago
• vortexgpgpu / vortex
  ☆1,655Updated last week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,082Updated 9 months ago
• asicguy / gplgpu
  GPL v3 2D/3D graphics engine in verilog
  ☆671Updated 11 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,969Updated 4 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆553Updated 3 weeks ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆974Updated last year
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆602Updated 2 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated last week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆873Updated 5 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,459Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆729Updated 2 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆896Updated 4 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,611Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,959Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,339Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,091Updated 3 years ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,311Updated last year
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,171Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,117Updated 3 months ago
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,045Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,872Updated 2 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,628Updated last week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆736Updated 3 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆858Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,166Updated 3 months ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,396Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆731Updated 3 weeks ago