An open source GPU based off of the AMD Southern Islands ISA.
☆1,379Aug 18, 2025Updated 9 months ago
Alternatives and similar repositories for miaow
Users that are interested in miaow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,327Nov 22, 2024Updated last year
- GPGPU microprocessor architecture☆2,195Nov 8, 2024Updated last year
- ☆2,092Updated this week
- GPL v3 2D/3D graphics engine in verilog☆701Aug 31, 2014Updated 11 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆915Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RTL, Cmodel, and testbench for NVDLA☆2,102Mar 2, 2022Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆119May 11, 2023Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,960Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,203Jun 27, 2024Updated last year
- ☆224May 11, 2026Updated last month
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆379Jul 12, 2017Updated 8 years ago
- Rocket Chip Generator☆3,792Jun 2, 2026Updated last week
- MIAOW2.0 FPGA implementable design☆12Oct 18, 2017Updated 8 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 14 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆982Nov 15, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,159Feb 11, 2026Updated 4 months ago
- The OpenPiton Platform☆794Feb 25, 2026Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,174Mar 11, 2026Updated 3 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆585Jun 6, 2026Updated last week
- A minimal GPU design in Verilog to learn how GPUs work from the ground up☆12,569Aug 18, 2024Updated last year
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,640Feb 15, 2025Updated last year
- Verilog library for ASIC and FPGA designers☆1,421May 8, 2024Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,243May 29, 2026Updated 2 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tile based architecture designed for computing efficiency, scalability and generality☆294Updated this week
- Yosys Open SYnthesis Suite☆4,513Jun 7, 2026Updated last week
- An open-source microcontroller system based on RISC-V☆1,040Feb 6, 2024Updated 2 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,568May 12, 2026Updated last month
- VeeR EH1 core☆949May 29, 2023Updated 3 years ago
- A Linux-capable RISC-V multicore for and by the world☆811Jun 5, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,181Feb 21, 2026Updated 3 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- 32-bit Superscalar RISC-V CPU☆1,259Sep 18, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Chisel: A Modern Hardware Design Language☆4,680Jun 4, 2026Updated last week
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆236Dec 22, 2025Updated 5 months ago
- A small, light weight, RISC CPU soft core☆1,550Dec 8, 2025Updated 6 months ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 7 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆613May 26, 2026Updated 2 weeks ago
- A directory of Western Digital’s RISC-V SweRV Cores☆881Mar 26, 2020Updated 6 years ago
- RISC-V CPU Core☆434Jun 24, 2025Updated 11 months ago