An open source GPU based off of the AMD Southern Islands ISA.
☆1,426Aug 18, 2025Updated last year
Alternatives and similar repositories for miaow
Users that are interested in miaow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,392Nov 22, 2024Updated last year
- GPGPU microprocessor architecture☆2,228Nov 8, 2024Updated last year
- ☆2,313Updated this week
- GPL v3 2D/3D graphics engine in verilog☆703Aug 31, 2014Updated 12 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆957Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RTL, Cmodel, and testbench for NVDLA☆2,183Mar 2, 2022Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆123May 11, 2023Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,157Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,390Sep 7, 2026Updated last month
- Rocket Chip Generator☆3,885Sep 13, 2026Updated last month
- ☆241Aug 22, 2026Updated last month
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆387Jul 12, 2017Updated 9 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,259Updated this week
- MIAOW2.0 FPGA implementable design☆12Oct 18, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,007Nov 15, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,285Updated this week
- The OpenPiton Platform☆833Feb 25, 2026Updated 7 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆593Jun 6, 2026Updated 4 months ago
- A directory of Western Digital’s RISC-V SweRV Cores☆883Mar 26, 2020Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,442May 8, 2024Updated 2 years ago
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,749Oct 3, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated 3 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,314Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- An open-source microcontroller system based on RISC-V☆1,070Feb 6, 2024Updated 2 years ago
- Yosys Open SYnthesis Suite☆4,805Updated this week
- A minimal GPU design in Verilog to learn how GPUs work from the ground up☆13,090Aug 18, 2024Updated 2 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,623Updated this week
- VeeR EH1 core☆970Jul 16, 2026Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆835Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,721Sep 24, 2026Updated 2 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,212Oct 3, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,315Sep 18, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel: A Modern Hardware Design Language☆4,808Updated this week
- A small, light weight, RISC CPU soft core☆1,592Sep 16, 2026Updated 3 weeks ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆240Dec 22, 2025Updated 9 months ago
- Experiments with fixed function renderers and ChiselHDL☆61Oct 6, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆644Sep 14, 2026Updated 3 weeks ago
- RISC-V CPU Core☆453Jun 24, 2025Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆172Jul 3, 2020Updated 6 years ago