Alternatives and similar repositories for wujian100_open

Users that are interested in wujian100_open are comparing it to the libraries listed below

• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,725Updated 4 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,524Updated 8 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,281Updated 11 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆887Updated 4 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,923Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 3 weeks ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,168Updated 2 years ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,473Updated 3 weeks ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,797Updated 2 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,481Updated 3 years ago
• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,465Updated 5 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,877Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,570Updated this week
• cnrv / home
  为推广RISC-V尽些薄力
  ☆311Updated 2 years ago
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆967Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,041Updated 3 years ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,349Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆417Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,082Updated last month
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,808Updated 2 weeks ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,746Updated 3 months ago
• nvdla / hw
  RTL, Cmodel, and testbench for NVDLA
  ☆1,899Updated 3 years ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,537Updated 11 months ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆754Updated this week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,359Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆813Updated 3 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆730Updated 3 years ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,801Updated last week