XUANTIE-RV / wujian100_open
IC design and development should be faster,simpler and more reliable
☆1,892Updated 3 years ago
Alternatives and similar repositories for wujian100_open:
Users that are interested in wujian100_open are comparing it to the libraries listed below
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,661Updated 3 years ago
- The Ultra-Low Power RISC-V Core☆1,401Updated 4 months ago
- OpenXuantie - OpenC910 Core☆1,218Updated 7 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,151Updated 2 years ago
- RTL, Cmodel, and testbench for NVDLA☆1,815Updated 2 years ago
- RISC-V Cores, SoC platforms and SoCs☆859Updated 3 years ago
- Must-have verilog systemverilog modules☆1,716Updated 3 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆903Updated last month
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,808Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,750Updated this week
- 关于RISC-V你所需要知道的一切☆551Updated last year
- 为推广RISC-V尽些薄力☆309Updated last year
- Random instruction generator for RISC-V processor verification☆1,065Updated 2 weeks ago
- Verilog AXI components for FPGA implementation☆1,609Updated last year
- RISC-V CPU Core (RV32IM)☆1,359Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,010Updated 5 months ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,379Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,207Updated this week
- Rocket Chip Generator☆3,350Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,203Updated 2 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,471Updated this week
- Source files for SiFive's Freedom platforms☆1,113Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,288Updated 7 months ago
- 中文版 Parallel Programming for FPGAs☆718Updated 6 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,665Updated last week
- LicheeTang 蜂鸟E203 Core☆189Updated 5 years ago
- Verilog library for ASIC and FPGA designers☆1,248Updated 9 months ago
- chisel tutorial exercises and answers☆710Updated 3 years ago
- VeeR EH1 core☆846Updated last year
- Verilog PCI express components☆1,211Updated 9 months ago