Alternatives and similar repositories for wujian100_open:

Users that are interested in wujian100_open are comparing it to the libraries listed below

• SI-RISCV / e200_opensource
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,706Updated 4 years ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,470Updated 6 months ago
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,260Updated 9 months ago
• cnrv / home
  为推广RISC-V尽些薄力
  ☆312Updated last year
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆871Updated 4 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,160Updated 2 years ago
• nvdla / hw
  RTL, Cmodel, and testbench for NVDLA
  ☆1,859Updated 3 years ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,761Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆869Updated last year
• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆556Updated 2 years ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,684Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,097Updated 2 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,817Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,430Updated 9 months ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,416Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,284Updated last week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,422Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,256Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,514Updated 2 weeks ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆412Updated this week
• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,449Updated 3 months ago
• xupsh / pp4fpgas-cn
  中文版 Parallel Programming for FPGAs
  ☆723Updated 8 months ago
• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆194Updated 5 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆994Updated 3 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,865Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,049Updated 2 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,385Updated 2 months ago
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,214Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,440Updated last week