chipsalliance / Cores-VeeR-EL2Links
VeeR EL2 Core
☆297Updated this week
Alternatives and similar repositories for Cores-VeeR-EL2
Users that are interested in Cores-VeeR-EL2 are comparing it to the libraries listed below
Sorting:
- RISC-V Debug Support for our PULP RISC-V Cores☆273Updated last week
- ☆244Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆324Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated 2 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 4 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- CORE-V Family of RISC-V Cores☆299Updated 7 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆245Updated 10 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- RISC-V CPU Core☆387Updated 3 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆440Updated 4 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆599Updated last week
- SystemRDL 2.0 language compiler front-end☆261Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆294Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆286Updated this week
- Verilog Configurable Cache☆183Updated 10 months ago
- ☆297Updated last week
- RISC-V Torture Test☆197Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- Common SystemVerilog components☆660Updated last week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆349Updated 7 months ago
- ☆145Updated last year
- ☆189Updated last year
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- RISC-V microcontroller IP core developed in Verilog☆183Updated 5 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
- Basic RISC-V Test SoC☆144Updated 6 years ago