VeeR EL2 Core
☆336May 6, 2026Updated this week
Alternatives and similar repositories for Cores-VeeR-EL2
Users that are interested in Cores-VeeR-EL2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆265Dec 22, 2022Updated 3 years ago
- VeeR EH1 core☆939May 29, 2023Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆340Dec 11, 2024Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆980Nov 15, 2024Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,868Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆1,241Sep 18, 2021Updated 4 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,226Apr 17, 2026Updated 3 weeks ago
- ☆155Oct 6, 2023Updated 2 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆881Mar 26, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆203Apr 3, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,922Updated this week
- SERV - The SErial RISC-V CPU☆1,793Feb 19, 2026Updated 2 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆233Aug 25, 2020Updated 5 years ago
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆31Dec 9, 2021Updated 4 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆677Apr 16, 2026Updated 3 weeks ago
- ☆314Jan 23, 2026Updated 3 months ago
- Common SystemVerilog components☆743May 5, 2026Updated last week
- FuseSoC standard core library☆163Apr 28, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RISC-V CPU Core☆427Jun 24, 2025Updated 10 months ago
- A Linux-capable RISC-V multicore for and by the world☆800Apr 24, 2026Updated 2 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆518Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆309Apr 1, 2026Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,171Feb 21, 2026Updated 2 months ago
- The OpenPiton Platform☆788Feb 25, 2026Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- RISC-V Formal Verification Framework☆630Apr 6, 2022Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,568Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆186Apr 4, 2026Updated last month
- RISC-V Cores, SoC platforms and SoCs☆922Mar 26, 2021Updated 5 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 8 months ago
- Random instruction generator for RISC-V processor verification☆1,295Apr 3, 2026Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- Processor support packages☆20Feb 2, 2021Updated 5 years ago