chipsalliance / Cores-VeeR-EL2
VeeR EL2 Core
☆274Updated last week
Alternatives and similar repositories for Cores-VeeR-EL2:
Users that are interested in Cores-VeeR-EL2 are comparing it to the libraries listed below
- FuseSoC-based SoC for VeeR EH1 and EL2☆315Updated 4 months ago
- ☆232Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆250Updated 2 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆485Updated 2 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆528Updated 3 weeks ago
- Common SystemVerilog components☆608Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆231Updated 6 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆210Updated 3 weeks ago
- RISC-V CPU Core☆324Updated 10 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated this week
- CORE-V Family of RISC-V Cores☆264Updated 2 months ago
- ☆283Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆255Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆420Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆318Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆226Updated 5 months ago
- ☆321Updated 7 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆570Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- Fabric generator and CAD tools☆178Updated 2 weeks ago
- Verilog Configurable Cache☆178Updated 5 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆278Updated last week
- RISC-V Torture Test☆193Updated 9 months ago
- RISC-V microcontroller IP core developed in Verilog☆175Updated 3 weeks ago
- SystemC/TLM-2.0 Co-simulation framework☆240Updated 6 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated 8 months ago