GPGPU microprocessor architecture
☆2,180Nov 8, 2024Updated last year
Alternatives and similar repositories for NyuziProcessor
Users that are interested in NyuziProcessor are comparing it to the libraries listed below
Sorting:
- An open source GPU based off of the AMD Southern Islands ISA.☆1,342Aug 18, 2025Updated 6 months ago
- ☆1,913Updated this week
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,273Nov 22, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,027Mar 2, 2022Updated 4 years ago
- GPL v3 2D/3D graphics engine in verilog☆689Aug 31, 2014Updated 11 years ago
- Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture☆65Dec 4, 2022Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 3 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆875Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,153Feb 21, 2026Updated 2 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,498Jan 7, 2026Updated 2 months ago
- The OpenPiton Platform☆774Feb 25, 2026Updated last week
- Build your hardware, easily!☆3,747Updated this week
- Verilog library for ASIC and FPGA designers☆1,395May 8, 2024Updated last year
- Rocket Chip Generator☆3,705Feb 25, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,316Updated this week
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,761Feb 19, 2026Updated 2 weeks ago
- GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for…☆1,578Feb 15, 2025Updated last year
- Chisel: A Modern Hardware Design Language☆4,598Feb 28, 2026Updated last week
- An open-source microcontroller system based on RISC-V☆1,010Feb 6, 2024Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,083Feb 5, 2026Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆964Nov 15, 2024Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,391Feb 13, 2026Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- Must-have verilog systemverilog modules☆1,935Feb 19, 2026Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated 2 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,160Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- VRoom! RISC-V CPU☆518Sep 2, 2024Updated last year
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,785Feb 17, 2026Updated 2 weeks ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,210Updated this week
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- Scala based HDL☆1,929Updated this week
- An Open-source FPGA IP Generator☆1,057Updated this week