openhwgroup / cv32e40p

Related projects ⓘ

Alternatives and complementary repositories for cv32e40p

• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,026Updated 2 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆822Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,381Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,112Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆865Updated 3 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆866Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆452Updated 7 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆626Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆446Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆585Updated 2 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆839Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆389Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆643Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆688Updated 3 months ago
• riscv-non-isa / riscv-arch-test
  ☆516Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆497Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆771Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆544Updated 3 months ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆696Updated 2 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆459Updated 2 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆291Updated 2 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,272Updated 3 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆710Updated 3 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,205Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• riscv-software-src / riscv-tests
  ☆898Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆562Updated 3 weeks ago