Alternatives and similar repositories for cv32e40p

Users that are interested in cv32e40p are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆883Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,308Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,041Updated 3 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆887Updated 4 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆918Updated 7 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆559Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆711Updated last month
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆639Updated last month
• riscv-non-isa / riscv-arch-test
  ☆567Updated this week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆709Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆497Updated 6 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,481Updated 3 years ago
• riscv-software-src / riscv-tests
  ☆1,024Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆581Updated 10 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆504Updated 4 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆813Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆436Updated last week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,746Updated 3 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,300Updated this week