Alternatives and similar repositories for cv32e40p:

Users that are interested in cv32e40p are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆852Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆948Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,216Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,069Updated 3 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,478Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆644Updated 3 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆861Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆578Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆494Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆899Updated 3 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆701Updated 6 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆401Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆660Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆564Updated 6 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆810Updated 3 weeks ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,013Updated 5 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆475Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆943Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆516Updated 4 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,363Updated 3 weeks ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆745Updated 3 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆475Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆456Updated 2 weeks ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆712Updated 3 years ago
• riscv-non-isa / riscv-arch-test
  ☆540Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆313Updated 8 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,253Updated 9 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆522Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆551Updated this week