An open-source microcontroller system based on RISC-V
☆1,040Feb 6, 2024Updated 2 years ago
Alternatives and similar repositories for pulpino
Users that are interested in pulpino are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,243May 29, 2026Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆559Nov 26, 2024Updated last year
- RISC-V CPU Core☆434Jun 24, 2025Updated 11 months ago
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆483May 8, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,907Jun 3, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,188Jun 27, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,960Updated this week
- Rocket Chip Generator☆3,783Jun 2, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆982Nov 15, 2024Updated last year
- ☆23Mar 15, 2025Updated last year
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆379Jul 12, 2017Updated 8 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,159Feb 11, 2026Updated 3 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆162Feb 28, 2018Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated 3 weeks ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,845Mar 24, 2021Updated 5 years ago
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- VeeR EH1 core☆949May 29, 2023Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,174Mar 11, 2026Updated 2 months ago
- GPGPU microprocessor architecture☆2,195Nov 8, 2024Updated last year
- educational microarchitectures for risc-v isa☆748Sep 1, 2025Updated 9 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,098Mar 2, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆422Updated this week
- Z-scale Microarchitectural Implementation of RV32 ISA☆55May 30, 2017Updated 9 years ago
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 6 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,280Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆684May 27, 2026Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,561May 12, 2026Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆311Apr 1, 2026Updated 2 months ago
- RISC-V Formal Verification Framework☆631Apr 6, 2022Updated 4 years ago
- Yosys Open SYnthesis Suite☆4,513Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆106Aug 19, 2025Updated 9 months ago
- Common SystemVerilog components☆755Updated this week
- An open source GPU based off of the AMD Southern Islands ISA.☆1,379Aug 18, 2025Updated 9 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆687Jul 16, 2025Updated 10 months ago
- The OpenPiton Platform☆792Feb 25, 2026Updated 3 months ago
- Verilog library for ASIC and FPGA designers☆1,420May 8, 2024Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆609May 26, 2026Updated 2 weeks ago