pulp-platform / pulpino
An open-source microcontroller system based on RISC-V
☆954Updated last year
Alternatives and similar repositories for pulpino
Users that are interested in pulpino are comparing it to the libraries listed below
Sorting:
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,535Updated last week
- The root repo for lowRISC project and FPGA demos.☆598Updated last year
- VeeR EH1 core☆875Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,065Updated 3 months ago
- Verilog library for ASIC and FPGA designers☆1,282Updated last year
- A small, light weight, RISC CPU soft core☆1,398Updated 3 months ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,459Updated this week
- educational microarchitectures for risc-v isa☆713Updated 2 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆652Updated 6 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆533Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆914Updated 6 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,281Updated 3 weeks ago
- SERV - The SErial RISC-V CPU☆1,578Updated this week
- A directory of Western Digital’s RISC-V SweRV Cores☆865Updated 5 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,886Updated last week
- Random instruction generator for RISC-V processor verification☆1,113Updated 3 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,756Updated 3 weeks ago
- RISC-V Cores, SoC platforms and SoCs☆875Updated 4 years ago
- chisel tutorial exercises and answers☆724Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,473Updated 10 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,309Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,844Updated this week
- 32-bit Superscalar RISC-V CPU☆1,014Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆422Updated 2 months ago
- Support for Rocket Chip on Zynq FPGAs☆407Updated 6 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆490Updated 5 months ago
- The OpenPiton Platform☆702Updated 2 months ago
- RISC-V Tools (ISA Simulator and Tests)☆1,165Updated 2 years ago
- RISC-V Formal Verification Framework☆601Updated 3 years ago
- Linux on LiteX-VexRiscv☆635Updated this week