Alternatives and similar repositories for pulpino

Users that are interested in pulpino are comparing it to the libraries listed below

• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• lowRISC / lowrisc-chip
  The root repo for lowRISC project and FPGA demos.
  ☆601Updated 2 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆922Updated 2 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,751Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆574Updated 5 months ago
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆881Updated 5 years ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,791Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆734Updated 5 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,504Updated 2 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆909Updated 4 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,385Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆960Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,248Updated 4 months ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆415Updated 7 years ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,485Updated last month
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆743Updated 4 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆766Updated 4 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,067Updated 2 weeks ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,999Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆623Updated 3 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆457Updated 8 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆894Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,174Updated 3 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,107Updated last year
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,133Updated this week