The OpenPiton Platform
☆838Oct 30, 2026Updated this week
Alternatives and similar repositories for openpiton
Users that are interested in openpiton are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,184Updated this week
- A Linux-capable RISC-V multicore for and by the world☆840Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆305Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆433Oct 27, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Random instruction generator for RISC-V processor verification☆1,375Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,442Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,214Updated this week
- VeeR EH1 core☆971Jul 16, 2026Updated 3 months ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,742Updated this week
- Rocket Chip Generator☆3,895Sep 13, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆648Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆244Nov 20, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Common SystemVerilog components☆812Sep 18, 2026Updated last month
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,147Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,275Oct 8, 2026Updated 3 weeks ago
- VeeR EH2 core☆283Oct 6, 2026Updated 3 weeks ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,013Nov 15, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,316Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆737Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,058Oct 26, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,301Oct 13, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RTL, Cmodel, and testbench for NVDLA☆2,195Mar 2, 2022Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,329Sep 18, 2021Updated 5 years ago
- VeeR EL2 Core☆349Updated this week
- ☆394Aug 19, 2026Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,912Aug 25, 2026Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆561Oct 16, 2026Updated 2 weeks ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- The OpenPiton Platform☆32May 22, 2023Updated 3 years ago
- ☆2,372Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Chisel RTL generator for network-on-chip interconnects☆239Nov 7, 2025Updated 11 months ago
- GPGPU microprocessor architecture☆2,232Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,479Oct 23, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated last month
- A Fast, Low-Overhead On-chip Network☆371Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago