The OpenPiton Platform
☆828Feb 25, 2026Updated 6 months ago
Alternatives and similar repositories for openpiton
Users that are interested in openpiton are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,127Updated this week
- A Linux-capable RISC-V multicore for and by the world☆833Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆303Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆425Sep 16, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆684Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- VeeR EH1 core☆970Jul 16, 2026Updated 2 months ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,392Updated this week
- Random instruction generator for RISC-V processor verification☆1,357Updated this week
- VeeR EH2 core☆280Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆244Nov 20, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,202Updated this week
- Rocket Chip Generator☆3,868Sep 13, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,240Sep 11, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Sep 14, 2026Updated last week
- The OpenPiton Platform☆33May 22, 2023Updated 3 years ago
- GPGPU microprocessor architecture☆2,224Nov 8, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,002Nov 15, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,704Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,063Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,293Aug 26, 2026Updated 3 weeks ago
- ☆393Aug 19, 2026Updated last month
- 32-bit Superscalar RISC-V CPU☆1,309Sep 18, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,043Sep 10, 2026Updated last week
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago
- VeeR EL2 Core☆345Updated this week
- Common SystemVerilog components☆800Updated this week
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,268Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆467Sep 10, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,166Mar 2, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SERV - The SErial RISC-V CPU☆1,887Aug 25, 2026Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆326Aug 7, 2026Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆237Nov 7, 2025Updated 10 months ago
- Flexible Intermediate Representation for RTL☆746Aug 20, 2024Updated 2 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆723Sep 14, 2026Updated last week
- An open-source static random access memory (SRAM) compiler.☆1,136Aug 16, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,462Sep 12, 2026Updated last week