Alternatives and similar repositories for openpiton:

Users that are interested in openpiton are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆848Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆658Updated last week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,010Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆943Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆572Updated 2 weeks ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆700Updated 6 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆592Updated 2 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆399Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆559Updated 6 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆551Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆455Updated last week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆513Updated 4 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,204Updated 3 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,471Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,750Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆802Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,066Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆473Updated 2 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆737Updated 6 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆873Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆272Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆591Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆641Updated 3 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆898Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆311Updated 8 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆493Updated this week
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆356Updated this week
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆711Updated 3 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆263Updated this week