PrincetonUniversity / openpitonLinks
The OpenPiton Platform
☆723Updated 2 weeks ago
Alternatives and similar repositories for openpiton
Users that are interested in openpiton are comparing it to the libraries listed below
Sorting:
- A Linux-capable RISC-V multicore for and by the world☆719Updated 3 months ago
- VeeR EH1 core☆885Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆595Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,101Updated 2 months ago
- Common SystemVerilog components☆642Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆572Updated last week
- A directory of Western Digital’s RISC-V SweRV Cores☆871Updated 5 years ago
- SystemVerilog to Verilog conversion☆653Updated last month
- An open-source static random access memory (SRAM) compiler.☆933Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆436Updated 2 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated 3 weeks ago
- Random instruction generator for RISC-V processor verification☆1,146Updated 2 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆506Updated 8 months ago
- 32-bit Superscalar RISC-V CPU☆1,069Updated 3 years ago
- educational microarchitectures for risc-v isa☆718Updated 5 months ago
- RISC-V Formal Verification Framework☆607Updated 3 years ago
- ☆580Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,600Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆451Updated last week
- mor1kx - an OpenRISC 1000 processor IP core☆549Updated 2 weeks ago
- RISC-V CPU Core☆363Updated last month
- Instruction Set Generator initially contributed by Futurewei☆290Updated last year
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆475Updated last year
- RISC-V Cores, SoC platforms and SoCs☆895Updated 4 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- Simple RISC-V 3-stage Pipeline in Chisel☆585Updated 11 months ago
- Flexible Intermediate Representation for RTL☆748Updated 11 months ago
- Digital Design with Chisel☆852Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,343Updated this week