user-xleo / DNN-AcceleratorLinks
A DNN Accelerator implemented with RTL.
☆64Updated 5 months ago
Alternatives and similar repositories for DNN-Accelerator
Users that are interested in DNN-Accelerator are comparing it to the libraries listed below
Sorting:
- ☆112Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆78Updated 4 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- ☆65Updated 6 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- ☆10Updated 3 years ago
- ☆46Updated 7 years ago
- 中文:☆101Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆37Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆39Updated 11 months ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month