user-xleo / DNN-AcceleratorLinks
A DNN Accelerator implemented with RTL.
☆67Updated 7 months ago
Alternatives and similar repositories for DNN-Accelerator
Users that are interested in DNN-Accelerator are comparing it to the libraries listed below
Sorting:
- ☆113Updated 5 years ago
- 中文:☆101Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆190Updated 7 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆129Updated 3 months ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆185Updated last year
- ☆47Updated 7 years ago
- FPGA☆158Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆27Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆95Updated last month
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆50Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago