heheda365 / ultra_netLinks
FPGA-based neural network inference project for 2020 DAC System Design Contest
☆113Updated 4 years ago
Alternatives and similar repositories for ultra_net
Users that are interested in ultra_net are comparing it to the libraries listed below
Sorting:
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 6 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 6 months ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆46Updated 7 years ago
- 中文:☆101Updated 5 years ago
- XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.☆183Updated last year
- ☆33Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆27Updated 4 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆11Updated last year
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Deep Learning Accelerator (Convolution Neural Networks)