DMA core compatible with AHB3-Lite
☆13Mar 30, 2019Updated 7 years ago
Alternatives and similar repositories for ahb3lite_dma
Users that are interested in ahb3lite_dma are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 10 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆13Sep 7, 2018Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Fusesoc compatible rtl cores☆18Sep 9, 2026Updated last month
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- AXI4 to SRAM Interface☆13May 2, 2022Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- A simple UVM project. The DUT(RTL) is a simple amplifier.☆10Sep 28, 2022Updated 4 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 4 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- USB 1.1 PHY☆12Jul 17, 2014Updated 12 years ago
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆13Jun 22, 2023Updated 3 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- verilog/FPGA hardware description for very simple GPU☆17Apr 9, 2019Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆28Oct 19, 2026Updated last week
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- AHB DMA 32 / 64 bits☆64Jul 17, 2014Updated 12 years ago
- AHB3-Lite Interconnect☆110May 10, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs☆11Jun 19, 2020Updated 6 years ago
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 13 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 12 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- Audio DSP on an FPGA using eurorack-pmod + LiteX with firmware in Rust.☆19Oct 7, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- USB-PD-3.1-Verilog☆17Apr 22, 2024Updated 2 years ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- RTL code of some arbitration algorithm☆16Oct 10, 2026Updated 2 weeks ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆16Aug 7, 2022Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago