vfinotti / ahb3lite_dma
DMA core compatible with AHB3-Lite
☆10Updated 6 years ago
Alternatives and similar repositories for ahb3lite_dma
Users that are interested in ahb3lite_dma are comparing it to the libraries listed below
Sorting:
- ☆16Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- ☆12Updated 9 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆19Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆21Updated 5 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- ☆10Updated 4 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- AXI4 with a FIFO integrated with VIP☆18Updated last year
- ☆25Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆17Updated 10 years ago
- ☆19Updated 2 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- commit rtl and build cosim env☆15Updated last year
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- Verification IP for UART protocol☆16Updated 4 years ago
- Various low power labs using sky130☆12Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆14Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Direct Access Memory for MPSoC☆12Updated this week