yuehniu / CNN.frequencyFPGA
CNN Accelerator in Frequency Domain
☆12Updated 4 years ago
Alternatives and similar repositories for CNN.frequencyFPGA:
Users that are interested in CNN.frequencyFPGA are comparing it to the libraries listed below
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆13Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆35Updated 2 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- ☆33Updated 5 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆38Updated 4 months ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 8 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Updated 4 years ago
- ☆19Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- ☆26Updated 2 years ago
- ☆24Updated 5 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆12Updated 7 months ago
- ☆18Updated 2 years ago