yuehniu / CNN.frequencyFPGALinks
CNN Accelerator in Frequency Domain
☆12Updated 5 years ago
Alternatives and similar repositories for CNN.frequencyFPGA
Users that are interested in CNN.frequencyFPGA are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆34Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- 2020 xilinx summer school☆17Updated 5 years ago
- ☆72Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆28Updated 5 months ago
- ☆27Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆53Updated 3 years ago
- ☆18Updated 2 years ago
- ☆17Updated 4 months ago
- ☆21Updated 2 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 4 years ago
- ☆66Updated 6 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- ☆60Updated 5 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- ☆26Updated 2 years ago
- ☆17Updated 2 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago