thedatabusdotio / fpga-ml-acceleratorLinks
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
☆154Updated last year
Alternatives and similar repositories for fpga-ml-accelerator
Users that are interested in fpga-ml-accelerator are comparing it to the libraries listed below
Sorting:
- Convolutional accelerator kernel, target ASIC & FPGA☆211Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆162Updated 5 years ago
- Implementation of CNN using Verilog☆218Updated 7 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- IC implementation of Systolic Array for TPU☆251Updated 8 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆180Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆186Updated 7 years ago
- Convolutional Neural Network RTL-level Design☆58Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month
- AXI总线连接器☆99Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆157Updated last week