8krisv / CNN-ACCELERATORLinks
Hardware accelerator for convolutional neural networks
☆45Updated 2 years ago
Alternatives and similar repositories for CNN-ACCELERATOR
Users that are interested in CNN-ACCELERATOR are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆111Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- ☆65Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 10 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆56Updated 4 months ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- ☆15Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 8 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆39Updated 4 years ago
- ☆33Updated 6 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago