8krisv / CNN-ACCELERATORLinks
Hardware accelerator for convolutional neural networks
☆59Updated 3 years ago
Alternatives and similar repositories for CNN-ACCELERATOR
Users that are interested in CNN-ACCELERATOR are comparing it to the libraries listed below
Sorting:
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- ☆120Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆118Updated 3 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆176Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆138Updated 6 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆33Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- ☆71Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆155Updated 8 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- ☆42Updated 4 years ago
- Verilog implementation of Softmax function☆75Updated 3 years ago
- This repository contains full code of Softmax Layer in Verilog☆20Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆106Updated 10 months ago
- A collection of tutorials for the fpgaConvNet framework.☆46Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- IC implementation of TPU☆135Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆234Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆195Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆137Updated 9 months ago
- A DNN Accelerator implemented with RTL.☆68Updated 10 months ago