sandy2008 / CNN-FPGALinks
☆19Updated 6 years ago
Alternatives and similar repositories for CNN-FPGA
Users that are interested in CNN-FPGA are comparing it to the libraries listed below
Sorting:
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- ☆68Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆99Updated last year
- ☆36Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- ☆14Updated 2 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆26Updated 3 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆28Updated 6 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆12Updated last year