☆19Dec 19, 2018Updated 7 years ago
Alternatives and similar repositories for CNN-FPGA
Users that are interested in CNN-FPGA are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network (CNN) image classification of handwritten digits in Xilinx FPGA☆14Sep 12, 2019Updated 6 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year
- A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…☆12Jan 5, 2023Updated 3 years ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆164Dec 13, 2020Updated 5 years ago
- ESP32-NOW with Wifi☆23Apr 11, 2025Updated 10 months ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆22May 20, 2019Updated 6 years ago
- Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventio…☆17Jul 4, 2018Updated 7 years ago
- This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…☆18May 14, 2021Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- Final project for Computer Architecture FA16☆20Jan 5, 2017Updated 9 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Apr 24, 2019Updated 6 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Nov 5, 2021Updated 4 years ago
- Implementation of Sobel Filter in Verilog☆25Mar 10, 2017Updated 8 years ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆29Aug 17, 2021Updated 4 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Jan 9, 2019Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- A DNN Accelerator implemented with RTL.☆69Jan 9, 2025Updated last year
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆186Jan 28, 2017Updated 9 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- Simulating implement of LeNet network on Zynq-7020 FPGA☆30Mar 11, 2019Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆39Nov 24, 2022Updated 3 years ago
- IC Contest☆43Mar 28, 2023Updated 2 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Present Crypto Engine in Verilog☆11Feb 27, 2016Updated 10 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆581Jun 18, 2018Updated 7 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago