Alternatives and similar repositories for DCNN-Accelerator

Users that are interested in DCNN-Accelerator are comparing it to the libraries listed below

• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆51Updated 10 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆10Updated 3 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 8 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆15Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆27Updated 4 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆4Updated 4 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• dac-sdc / fpga_starter_2023
  ☆8Updated 2 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 7 months ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆21Updated 12 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆66Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆34Updated 6 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆31Updated 6 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆19Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆43Updated 10 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆46Updated 5 months ago
• abdelfattah-lab / BRAMAC
  ☆10Updated 8 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆87Updated 2 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆42Updated 2 months ago