Alternatives and similar repositories for SparseDNNAccelerator

Users that are interested in SparseDNNAccelerator are comparing it to the libraries listed below

• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆97Updated 4 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆32Updated 10 months ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆48Updated last year
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆56Updated 2 years ago
• CASR-HKU / DPACS
  ☆19Updated 2 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆124Updated 5 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆43Updated 2 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆18Updated last year
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆99Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆74Updated 3 months ago
• xliu0709 / DACSDC2021
  ☆11Updated last year
• Yang-YiFan / DiracDeltaNet
  PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
  ☆33Updated 6 years ago
• mean9park / BitFusion-verilog
  bitfusion verilog implementation
  ☆12Updated 3 years ago
• albertomarchisio / SwiftTron
  ☆46Updated 2 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆93Updated 3 years ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆122Updated last year
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆16Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆53Updated 7 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆20Updated 4 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆114Updated 4 years ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆18Updated last month
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆64Updated 3 years ago