Sparse CNN Accelerator targeting Intel FPGA
☆12Aug 26, 2021Updated 4 years ago
Alternatives and similar repositories for SparseDNNAccelerator
Users that are interested in SparseDNNAccelerator are comparing it to the libraries listed below
Sorting:
- ☆21Oct 26, 2022Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- Training Quantized Neural Networks with a Full-precision Auxiliary Module☆13Jun 19, 2020Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- ☆32Mar 31, 2025Updated 11 months ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- ☆19Mar 21, 2023Updated 2 years ago
- ☆17Nov 20, 2022Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- ☆124Jul 22, 2020Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆49Sep 20, 2024Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆65Aug 9, 2022Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Dec 21, 2020Updated 5 years ago
- ☆56Apr 19, 2023Updated 2 years ago
- ☆31Nov 7, 2024Updated last year
- ☆26Nov 4, 2022Updated 3 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Jul 12, 2018Updated 7 years ago
- A DNN Accelerator implemented with RTL.☆69Jan 9, 2025Updated last year
- ☆27Apr 28, 2020Updated 5 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆114Feb 22, 2021Updated 5 years ago
- Qimera: Data-free Quantization with Synthetic Boundary Supporting Samples [NeurIPS 2021]☆34Dec 12, 2021Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆198Dec 15, 2017Updated 8 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Oct 4, 2023Updated 2 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- ☆10Nov 22, 2022Updated 3 years ago
- ☆12Mar 12, 2022Updated 3 years ago
- yolov5-acceleration-fpga☆10Jun 25, 2025Updated 8 months ago
- ☆40Dec 10, 2019Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Code for reproducing the results from "CrAM: A Compression-Aware Minimizer" accepted at ICLR 2023