mustard-seed / SparseDNNAcceleratorLinks
Sparse CNN Accelerator targeting Intel FPGA
☆12Updated 3 years ago
Alternatives and similar repositories for SparseDNNAccelerator
Users that are interested in SparseDNNAccelerator are comparing it to the libraries listed below
Sorting:
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- ☆28Updated 4 months ago
- Open-source of MSD framework☆16Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆43Updated 10 months ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- ☆18Updated 2 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆24Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- RTL implementation of Flex-DPE.☆108Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- ☆113Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- ☆11Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆71Updated 5 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- bitfusion verilog implementation☆10Updated 3 years ago
- ☆21Updated 2 years ago
- ☆35Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- ☆14Updated 3 years ago