fffasttime / AnyPackingNet
☆25Updated last month
Alternatives and similar repositories for AnyPackingNet:
Users that are interested in AnyPackingNet are comparing it to the libraries listed below
- Open-source of MSD framework☆16Updated last year
- ☆19Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆36Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆13Updated 7 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆47Updated 2 weeks ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆21Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- ☆11Updated 10 months ago
- ☆12Updated last year
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆89Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆34Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated 3 weeks ago
- ☆18Updated 2 years ago
- ☆32Updated 4 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 2 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆14Updated 5 months ago
- A co-design architecture on sparse attention☆51Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆28Updated 6 months ago
- ☆69Updated 4 years ago
- ☆10Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 4 months ago
- ☆39Updated 7 months ago
- ☆71Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆28Updated 3 weeks ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago