fffasttime / AnyPackingNetLinks
☆28Updated 4 months ago
Alternatives and similar repositories for AnyPackingNet
Users that are interested in AnyPackingNet are comparing it to the libraries listed below
Sorting:
- ☆18Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆24Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆35Updated 5 years ago
- ☆72Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- ☆34Updated 6 years ago
- ☆21Updated 2 years ago
- ☆71Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆25Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- A collection of tutorials for the fpgaConvNet framework.☆43Updated 10 months ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 3 months ago
- ☆17Updated 2 months ago