fffasttime / AnyPackingNetLinks
☆27Updated 2 months ago
Alternatives and similar repositories for AnyPackingNet
Users that are interested in AnyPackingNet are comparing it to the libraries listed below
Sorting:
- Open-source of MSD framework☆16Updated last year
- ☆18Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆43Updated last year
- ☆12Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 10 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆34Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- ☆33Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆71Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- ☆41Updated 11 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆19Updated 9 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆27Updated last year
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- ☆10Updated 6 months ago
- Model LLM inference on single-core dataflow accelerators☆10Updated 3 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- ☆45Updated 3 years ago
- ☆16Updated 3 weeks ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago