Alternatives and similar repositories for AnyPackingNet

Users that are interested in AnyPackingNet are comparing it to the libraries listed below

• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆11Updated 3 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆43Updated last year
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 10 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• isakedo / DNNsim
  ☆34Updated 4 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆52Updated 3 years ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆77Updated 3 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 2 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated last month
• maestro-project / gamma
  ☆41Updated 11 months ago
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆19Updated 9 months ago
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆27Updated last year
• nimish15shah / DAG_Processor
  A DAG processor and compiler for a tree-based spatial datapath.
  ☆13Updated 2 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 3 years ago
• abdelfattah-lab / BRAMAC
  ☆10Updated 6 months ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 3 months ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆34Updated 3 years ago
• hatsu3 / Sanger
  ☆45Updated 3 years ago
• gem5-X / TiC-SAT
  ☆16Updated 3 weeks ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago