fffasttime / AnyPackingNetLinks
☆32Updated 10 months ago
Alternatives and similar repositories for AnyPackingNet
Users that are interested in AnyPackingNet are comparing it to the libraries listed below
Sorting:
- ☆19Updated 2 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆21Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- ☆35Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- ☆26Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Updated 2 years ago
- ☆71Updated 5 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆29Updated last year
- ☆35Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆72Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- MICRO22 artifact evaluation for Sparseloop☆47Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- 2020 xilinx summer school☆19Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆15Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 7 months ago
- ☆42Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆48Updated last year