pp-Innovate / FPGA-ZynqNetLinks
FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
☆112Updated 8 years ago
Alternatives and similar repositories for FPGA-ZynqNet
Users that are interested in FPGA-ZynqNet are comparing it to the libraries listed below
Sorting:
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆183Updated 8 years ago
- 中文:☆101Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- FPGA Accelerator for CNN using Vivado HLS☆319Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆143Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92Updated 6 years ago
- ☆47Updated 7 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆73Updated 7 years ago
- A convolutional neural network implemented in hardware (verilog)☆160Updated 7 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆238Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆190Updated 7 years ago
- ☆248Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 7 months ago
- Binarized Convolutional Neural Networks on Software-Programmable FPGAs☆308Updated 4 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago